/[dynamips]/trunk/mips64_exec.c
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upstream/dynamips-0.2.7-RC1/mips64_exec.c revision 7 by dpavlin, Sat Oct 6 16:23:47 2007 UTC trunk/mips64_exec.c revision 12 by dpavlin, Sat Oct 6 16:45:40 2007 UTC
# Line 51  void mips64_exec_create_ilt(void) Line 51  void mips64_exec_create_ilt(void)
51     for(i=0,count=0;mips64_exec_tags[i].exec;i++)     for(i=0,count=0;mips64_exec_tags[i].exec;i++)
52        count++;        count++;
53    
54     ilt = ilt_create(count+1,     ilt = ilt_create("mips64e",count,
55                      (ilt_get_insn_cbk_t)mips64_exec_get_insn,                      (ilt_get_insn_cbk_t)mips64_exec_get_insn,
56                      (ilt_check_cbk_t)mips64_exec_chk_lo,                      (ilt_check_cbk_t)mips64_exec_chk_lo,
57                      (ilt_check_cbk_t)mips64_exec_chk_hi);                      (ilt_check_cbk_t)mips64_exec_chk_hi);
# Line 279  void mips64_dump_insn_block(cpu_mips_t * Line 279  void mips64_dump_insn_block(cpu_mips_t *
279  }  }
280    
281  /* Execute a memory operation */  /* Execute a memory operation */
282  static forced_inline int mips64_exec_memop(cpu_mips_t *cpu,int memop,  static forced_inline void mips64_exec_memop(cpu_mips_t *cpu,int memop,
283                                             m_uint64_t vaddr,u_int dst_reg,                                              m_uint64_t vaddr,u_int dst_reg,
284                                             int keep_ll_bit)                                              int keep_ll_bit)
285  {      {    
286     fastcall mips_memop_fn fn;     fastcall mips_memop_fn fn;
287    
288     if (!keep_ll_bit) cpu->ll_bit = 0;     if (!keep_ll_bit) cpu->ll_bit = 0;
289     fn = cpu->mem_op_fn[memop];     fn = cpu->mem_op_fn[memop];
290     return(fn(cpu,vaddr,dst_reg));     fn(cpu,vaddr,dst_reg);
291  }  }
292    
293  /* Execute a memory operation (2) */  /* Execute a memory operation (2) */
294  static forced_inline int mips64_exec_memop2(cpu_mips_t *cpu,int memop,  static forced_inline void mips64_exec_memop2(cpu_mips_t *cpu,int memop,
295                                              m_uint64_t base,int offset,                                               m_uint64_t base,int offset,
296                                              u_int dst_reg,int keep_ll_bit)                                               u_int dst_reg,int keep_ll_bit)
297  {  {
298     m_uint64_t vaddr = cpu->gpr[base] + sign_extend(offset,16);     m_uint64_t vaddr = cpu->gpr[base] + sign_extend(offset,16);
299     fastcall mips_memop_fn fn;     fastcall mips_memop_fn fn;
300          
301     if (!keep_ll_bit) cpu->ll_bit = 0;     if (!keep_ll_bit) cpu->ll_bit = 0;
302     fn = cpu->mem_op_fn[memop];     fn = cpu->mem_op_fn[memop];
303     return(fn(cpu,vaddr,dst_reg));     fn(cpu,vaddr,dst_reg);
304  }  }
305    
306  /* Fetch an instruction */  /* Fetch an instruction */
# Line 322  static forced_inline int mips64_exec_fet Line 322  static forced_inline int mips64_exec_fet
322     return(0);     return(0);
323  }  }
324    
325    /* Unknown opcode */
326    static fastcall int mips64_exec_unknown(cpu_mips_t *cpu,mips_insn_t insn)
327    {
328       printf("MIPS64: unknown opcode 0x%8.8x at pc = 0x%llx\n",insn,cpu->pc);
329       mips64_dump_regs(cpu->gen);
330       return(0);
331    }
332    
333  /* Execute a single instruction */  /* Execute a single instruction */
334  static forced_inline int  static forced_inline int
335  mips64_exec_single_instruction(cpu_mips_t *cpu,mips_insn_t instruction)  mips64_exec_single_instruction(cpu_mips_t *cpu,mips_insn_t instruction)
# Line 342  mips64_exec_single_instruction(cpu_mips_ Line 350  mips64_exec_single_instruction(cpu_mips_
350     tag = mips64_exec_get_insn(index);     tag = mips64_exec_get_insn(index);
351     exec = tag->exec;     exec = tag->exec;
352    
    if (likely(exec != NULL)) {  
353  #if NJM_STATS_ENABLE  #if NJM_STATS_ENABLE
354        cpu->insn_exec_count++;     cpu->insn_exec_count++;
355        mips64_exec_tags[index].count++;     mips64_exec_tags[index].count++;
356  #endif  #endif
357  #if 0  #if 0
358     {     {
359        char buffer[80];        char buffer[80];
360                
361        if (mips64_dump_insn(buffer,sizeof(buffer),0,cpu->pc,instruction)!=-1)        if (mips64_dump_insn(buffer,sizeof(buffer),0,cpu->pc,instruction)!=-1)
362           fprintf(log_file,"0x%llx: %s\n",cpu->pc,buffer);           cpu_log(cpu->gen,"EXEC","0x%llx: %s\n",cpu->pc,buffer);
363     }     }
364  #endif  #endif
365       return(exec(cpu,instruction));
       return(exec(cpu,instruction));  
    }  
   
    printf("MIPS64: unknown opcode 0x%8.8x at pc = 0x%llx\n",  
           instruction,cpu->pc);  
    mips64_dump_regs(cpu->gen);  
    return(0);  
366  }  }
367    
368  /* Single-step execution */  /* Single-step execution */
# Line 395  void *mips64_exec_run_cpu(cpu_gen_t *gen Line 395  void *mips64_exec_run_cpu(cpu_gen_t *gen
395     }     }
396    
397     gen->cpu_thread_running = TRUE;     gen->cpu_thread_running = TRUE;
398       cpu_exec_loop_set(gen);
399    
400   start_cpu:   start_cpu:
401     gen->idle_count = 0;     gen->idle_count = 0;
# Line 1075  static fastcall int mips64_exec_CACHE(cp Line 1076  static fastcall int mips64_exec_CACHE(cp
1076     int op     = bits(insn,16,20);     int op     = bits(insn,16,20);
1077     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1078    
1079     return(mips64_exec_memop2(cpu,MIPS_MEMOP_CACHE,base,offset,op,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_CACHE,base,offset,op,FALSE);
1080       return(0);
1081  }  }
1082    
1083  /* CFC0 */  /* CFC0 */
# Line 1393  static fastcall int mips64_exec_LB(cpu_m Line 1395  static fastcall int mips64_exec_LB(cpu_m
1395     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1396     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1397    
1398     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LB,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LB,base,offset,rt,TRUE);
1399       return(0);
1400  }  }
1401    
1402  /* LBU (Load Byte Unsigned) */  /* LBU (Load Byte Unsigned) */
# Line 1403  static fastcall int mips64_exec_LBU(cpu_ Line 1406  static fastcall int mips64_exec_LBU(cpu_
1406     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1407     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1408    
1409     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LBU,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LBU,base,offset,rt,TRUE);
1410       return(0);
1411  }  }
1412    
1413  /* LD (Load Double-Word) */  /* LD (Load Double-Word) */
# Line 1413  static fastcall int mips64_exec_LD(cpu_m Line 1417  static fastcall int mips64_exec_LD(cpu_m
1417     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1418     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1419    
1420     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LD,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LD,base,offset,rt,TRUE);
1421       return(0);
1422  }  }
1423    
1424  /* LDC1 (Load Double-Word to Coprocessor 1) */  /* LDC1 (Load Double-Word to Coprocessor 1) */
# Line 1423  static fastcall int mips64_exec_LDC1(cpu Line 1428  static fastcall int mips64_exec_LDC1(cpu
1428     int ft     = bits(insn,16,20);     int ft     = bits(insn,16,20);
1429     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1430    
1431     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LDC1,base,offset,ft,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LDC1,base,offset,ft,TRUE);
1432       return(0);
1433  }  }
1434    
1435  /* LDL (Load Double-Word Left) */  /* LDL (Load Double-Word Left) */
# Line 1433  static fastcall int mips64_exec_LDL(cpu_ Line 1439  static fastcall int mips64_exec_LDL(cpu_
1439     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1440     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1441    
1442     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LDL,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LDL,base,offset,rt,TRUE);
1443       return(0);
1444  }  }
1445    
1446  /* LDR (Load Double-Word Right) */  /* LDR (Load Double-Word Right) */
# Line 1443  static fastcall int mips64_exec_LDR(cpu_ Line 1450  static fastcall int mips64_exec_LDR(cpu_
1450     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1451     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1452    
1453     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LDR,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LDR,base,offset,rt,TRUE);
1454       return(0);
1455  }  }
1456    
1457  /* LH (Load Half-Word) */  /* LH (Load Half-Word) */
# Line 1453  static fastcall int mips64_exec_LH(cpu_m Line 1461  static fastcall int mips64_exec_LH(cpu_m
1461     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1462     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1463    
1464     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LH,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LH,base,offset,rt,TRUE);
1465       return(0);
1466  }  }
1467    
1468  /* LHU (Load Half-Word Unsigned) */  /* LHU (Load Half-Word Unsigned) */
# Line 1463  static fastcall int mips64_exec_LHU(cpu_ Line 1472  static fastcall int mips64_exec_LHU(cpu_
1472     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1473     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1474    
1475     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LHU,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LHU,base,offset,rt,TRUE);
1476       return(0);
1477  }  }
1478    
1479  /* LI (virtual) */  /* LI (virtual) */
# Line 1483  static fastcall int mips64_exec_LL(cpu_m Line 1493  static fastcall int mips64_exec_LL(cpu_m
1493     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1494     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1495    
1496     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LL,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LL,base,offset,rt,TRUE);
1497       return(0);
1498  }  }
1499    
1500  /* LUI */  /* LUI */
# Line 1503  static fastcall int mips64_exec_LW(cpu_m Line 1514  static fastcall int mips64_exec_LW(cpu_m
1514     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1515     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1516    
1517     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LW,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LW,base,offset,rt,TRUE);
1518       return(0);
1519  }  }
1520    
1521  /* LWL (Load Word Left) */  /* LWL (Load Word Left) */
# Line 1513  static fastcall int mips64_exec_LWL(cpu_ Line 1525  static fastcall int mips64_exec_LWL(cpu_
1525     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1526     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1527    
1528     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LWL,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LWL,base,offset,rt,TRUE);
1529       return(0);
1530  }  }
1531    
1532  /* LWR (Load Word Right) */  /* LWR (Load Word Right) */
# Line 1523  static fastcall int mips64_exec_LWR(cpu_ Line 1536  static fastcall int mips64_exec_LWR(cpu_
1536     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1537     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1538    
1539     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LWR,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LWR,base,offset,rt,TRUE);
1540       return(0);
1541  }  }
1542    
1543  /* LWU (Load Word Unsigned) */  /* LWU (Load Word Unsigned) */
# Line 1533  static fastcall int mips64_exec_LWU(cpu_ Line 1547  static fastcall int mips64_exec_LWU(cpu_
1547     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1548     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1549    
1550     return(mips64_exec_memop2(cpu,MIPS_MEMOP_LWU,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_LWU,base,offset,rt,TRUE);
1551       return(0);
1552  }  }
1553    
1554  /* MFC0 */  /* MFC0 */
# Line 1723  static fastcall int mips64_exec_SB(cpu_m Line 1738  static fastcall int mips64_exec_SB(cpu_m
1738     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1739     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1740    
1741     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SB,base,offset,rt,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SB,base,offset,rt,FALSE);
1742       return(0);
1743  }  }
1744    
1745  /* SC (Store Conditional) */  /* SC (Store Conditional) */
# Line 1733  static fastcall int mips64_exec_SC(cpu_m Line 1749  static fastcall int mips64_exec_SC(cpu_m
1749     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1750     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1751    
1752     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SC,base,offset,rt,TRUE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SC,base,offset,rt,TRUE);
1753       return(0);
1754  }  }
1755    
1756  /* SD (Store Double-Word) */  /* SD (Store Double-Word) */
# Line 1743  static fastcall int mips64_exec_SD(cpu_m Line 1760  static fastcall int mips64_exec_SD(cpu_m
1760     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1761     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1762    
1763     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SD,base,offset,rt,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SD,base,offset,rt,FALSE);
1764       return(0);
1765  }  }
1766    
1767  /* SDL (Store Double-Word Left) */  /* SDL (Store Double-Word Left) */
# Line 1753  static fastcall int mips64_exec_SDL(cpu_ Line 1771  static fastcall int mips64_exec_SDL(cpu_
1771     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1772     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1773        
1774     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SDL,base,offset,rt,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SDL,base,offset,rt,FALSE);
1775       return(0);
1776  }  }
1777    
1778  /* SDR (Store Double-Word Right) */  /* SDR (Store Double-Word Right) */
# Line 1763  static fastcall int mips64_exec_SDR(cpu_ Line 1782  static fastcall int mips64_exec_SDR(cpu_
1782     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1783     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1784    
1785     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SDR,base,offset,rt,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SDR,base,offset,rt,FALSE);
1786       return(0);
1787  }  }
1788    
1789  /* SDC1 (Store Double-Word from Coprocessor 1) */  /* SDC1 (Store Double-Word from Coprocessor 1) */
# Line 1773  static fastcall int mips64_exec_SDC1(cpu Line 1793  static fastcall int mips64_exec_SDC1(cpu
1793     int ft     = bits(insn,16,20);     int ft     = bits(insn,16,20);
1794     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1795    
1796     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SDC1,base,offset,ft,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SDC1,base,offset,ft,FALSE);
1797       return(0);
1798  }  }
1799    
1800  /* SH (Store Half-Word) */  /* SH (Store Half-Word) */
# Line 1783  static fastcall int mips64_exec_SH(cpu_m Line 1804  static fastcall int mips64_exec_SH(cpu_m
1804     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1805     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1806    
1807     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SH,base,offset,rt,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SH,base,offset,rt,FALSE);
1808       return(0);
1809  }  }
1810    
1811  /* SLL */  /* SLL */
# Line 1960  static fastcall int mips64_exec_SW(cpu_m Line 1982  static fastcall int mips64_exec_SW(cpu_m
1982     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1983     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1984    
1985     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SW,base,offset,rt,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SW,base,offset,rt,FALSE);
1986       return(0);
1987  }  }
1988    
1989  /* SWL (Store Word Left) */  /* SWL (Store Word Left) */
# Line 1970  static fastcall int mips64_exec_SWL(cpu_ Line 1993  static fastcall int mips64_exec_SWL(cpu_
1993     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
1994     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
1995        
1996     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SWL,base,offset,rt,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SWL,base,offset,rt,FALSE);
1997       return(0);
1998  }  }
1999    
2000  /* SWR (Store Word Right) */  /* SWR (Store Word Right) */
# Line 1980  static fastcall int mips64_exec_SWR(cpu_ Line 2004  static fastcall int mips64_exec_SWR(cpu_
2004     int rt     = bits(insn,16,20);     int rt     = bits(insn,16,20);
2005     int offset = bits(insn,0,15);     int offset = bits(insn,0,15);
2006    
2007     return(mips64_exec_memop2(cpu,MIPS_MEMOP_SWR,base,offset,rt,FALSE));     mips64_exec_memop2(cpu,MIPS_MEMOP_SWR,base,offset,rt,FALSE);
2008       return(0);
2009  }  }
2010    
2011  /* SYNC */  /* SYNC */
# Line 2196  static struct mips64_insn_exec_tag mips6 Line 2221  static struct mips64_insn_exec_tag mips6
2221     { "tlbwr"  , mips64_exec_TLBWR   , 0xffffffff , 0x42000006, 1, 1 },     { "tlbwr"  , mips64_exec_TLBWR   , 0xffffffff , 0x42000006, 1, 1 },
2222     { "xor"    , mips64_exec_XOR     , 0xfc0007ff , 0x00000026, 1, 3 },     { "xor"    , mips64_exec_XOR     , 0xfc0007ff , 0x00000026, 1, 3 },
2223     { "xori"   , mips64_exec_XORI    , 0xfc000000 , 0x38000000, 1, 5 },     { "xori"   , mips64_exec_XORI    , 0xfc000000 , 0x38000000, 1, 5 },
2224       { "unknown", mips64_exec_unknown , 0x00000000 , 0x00000000, 1, 0 },
2225     { NULL     , NULL                , 0x00000000 , 0x00000000, 1, 0 },     { NULL     , NULL                , 0x00000000 , 0x00000000, 1, 0 },
2226  };  };
2227    
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