1 |
/* |
2 |
* Cisco router simulation platform. |
3 |
* Copyright (c) 2007 Christophe Fillot (cf@utc.fr) |
4 |
* |
5 |
* Cisco C6k-SUP1 I/O FPGA: |
6 |
* - Simulates a NMC93C56 Serial EEPROM. |
7 |
* - Simulates a DALLAS DS1620 for Temperature Sensors. |
8 |
* - Simulates console and AUX ports (SCN2681). |
9 |
* |
10 |
* This is very similar to c7200 platform. |
11 |
*/ |
12 |
|
13 |
#include <stdio.h> |
14 |
#include <stdlib.h> |
15 |
#include <string.h> |
16 |
#include <unistd.h> |
17 |
#include <sys/types.h> |
18 |
|
19 |
#include <termios.h> |
20 |
#include <fcntl.h> |
21 |
#include <pthread.h> |
22 |
|
23 |
#include "ptask.h" |
24 |
#include "cpu.h" |
25 |
#include "vm.h" |
26 |
#include "dynamips.h" |
27 |
#include "memory.h" |
28 |
#include "device.h" |
29 |
#include "dev_vtty.h" |
30 |
#include "nmc93cX6.h" |
31 |
#include "ds1620.h" |
32 |
#include "dev_c6sup1.h" |
33 |
|
34 |
/* Debugging flags */ |
35 |
#define DEBUG_UNKNOWN 1 |
36 |
#define DEBUG_ACCESS 0 |
37 |
#define DEBUG_LED 0 |
38 |
#define DEBUG_IO_CTL 0 |
39 |
#define DEBUG_ENVM 0 |
40 |
|
41 |
/* DUART RX/TX status (SRA/SRB) */ |
42 |
#define DUART_RX_READY 0x01 |
43 |
#define DUART_TX_READY 0x04 |
44 |
|
45 |
/* DUART RX/TX Interrupt Status/Mask */ |
46 |
#define DUART_TXRDYA 0x01 |
47 |
#define DUART_RXRDYA 0x02 |
48 |
#define DUART_TXRDYB 0x10 |
49 |
#define DUART_RXRDYB 0x20 |
50 |
|
51 |
/* Definitions for CPU and Midplane Serial EEPROMs */ |
52 |
#define DO2_DATA_OUT_MIDPLANE 7 |
53 |
#define DO1_DATA_OUT_CPU 6 |
54 |
#define CS2_CHIP_SEL_MIDPLANE 5 |
55 |
#define SK2_CLOCK_MIDPLANE 4 |
56 |
#define DI2_DATA_IN_MIDPLANE 3 |
57 |
#define CS1_CHIP_SEL_CPU 2 |
58 |
#define SK1_CLOCK_CPU 1 |
59 |
#define DI1_DATA_IN_CPU 0 |
60 |
|
61 |
/* Pack the NVRAM */ |
62 |
#define NVRAM_PACKED 0x04 |
63 |
|
64 |
/* 2 temperature sensors in a MSFC1: chassis inlet and oulet */ |
65 |
#define C6SUP1_TEMP_SENSORS 2 |
66 |
#define C6SUP1_DEFAULT_TEMP 22 /* default temperature: 22°C */ |
67 |
|
68 |
/* IO FPGA structure */ |
69 |
struct iofpga_data { |
70 |
vm_obj_t vm_obj; |
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struct vdevice dev; |
72 |
c6sup1_t *router; |
73 |
|
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/* Lock test */ |
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pthread_mutex_t lock; |
76 |
|
77 |
/* Periodic task to trigger dummy DUART IRQ */ |
78 |
ptask_id_t duart_irq_tid; |
79 |
|
80 |
/* DUART & Console Management */ |
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u_int duart_isr,duart_imr,duart_irq_seq; |
82 |
|
83 |
/* IO control register */ |
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u_int io_ctrl_reg; |
85 |
|
86 |
/* Temperature Control */ |
87 |
u_int temp_cfg_reg[C6SUP1_TEMP_SENSORS]; |
88 |
u_int temp_deg_reg[C6SUP1_TEMP_SENSORS]; |
89 |
u_int temp_clk_low; |
90 |
|
91 |
u_int temp_cmd; |
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u_int temp_cmd_pos; |
93 |
|
94 |
u_int temp_data; |
95 |
u_int temp_data_pos; |
96 |
|
97 |
/* Voltages */ |
98 |
u_int mux; |
99 |
}; |
100 |
|
101 |
#define IOFPGA_LOCK(d) pthread_mutex_lock(&(d)->lock) |
102 |
#define IOFPGA_UNLOCK(d) pthread_mutex_unlock(&(d)->lock) |
103 |
|
104 |
/* Reset DS1620 */ |
105 |
static void temp_reset(struct iofpga_data *d) |
106 |
{ |
107 |
d->temp_cmd_pos = 0; |
108 |
d->temp_cmd = 0; |
109 |
|
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d->temp_data_pos = 0; |
111 |
d->temp_data = 0; |
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} |
113 |
|
114 |
/* Write the temperature control data */ |
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static void temp_write_ctrl(struct iofpga_data *d,u_char val) |
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{ |
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switch(val) { |
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case DS1620_RESET_ON: |
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temp_reset(d); |
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break; |
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|
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case DS1620_CLK_LOW: |
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d->temp_clk_low = 1; |
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break; |
125 |
|
126 |
case DS1620_CLK_HIGH: |
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d->temp_clk_low = 0; |
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break; |
129 |
} |
130 |
} |
131 |
|
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/* Read a temperature control data */ |
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static u_int temp_read_data(struct iofpga_data *d) |
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{ |
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u_int i,data = 0; |
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|
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switch(d->temp_cmd) { |
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case DS1620_READ_CONFIG: |
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for(i=0;i<C6SUP1_TEMP_SENSORS;i++) |
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data |= ((d->temp_cfg_reg[i] >> d->temp_data_pos) & 1) << i; |
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|
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d->temp_data_pos++; |
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|
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if (d->temp_data_pos == DS1620_CONFIG_READ_SIZE) |
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temp_reset(d); |
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|
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break; |
148 |
|
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case DS1620_READ_TEMP: |
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for(i=0;i<C6SUP1_TEMP_SENSORS;i++) |
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data |= ((d->temp_deg_reg[i] >> d->temp_data_pos) & 1) << i; |
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|
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d->temp_data_pos++; |
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|
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if (d->temp_data_pos == DS1620_DATA_READ_SIZE) |
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temp_reset(d); |
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|
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break; |
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|
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default: |
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vm_log(d->router->vm,"IO_FPGA","temp_sensors: CMD = 0x%x\n", |
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d->temp_cmd); |
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} |
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|
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return(data); |
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} |
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|
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/* Write the temperature data write register */ |
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static void temp_write_data(struct iofpga_data *d,u_char val) |
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{ |
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if (val == DS1620_ENABLE_READ) { |
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d->temp_data_pos = 0; |
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return; |
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} |
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|
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if (!d->temp_clk_low) |
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return; |
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|
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/* Write a command */ |
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if (d->temp_cmd_pos < DS1620_WRITE_SIZE) |
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{ |
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if (val == DS1620_DATA_HIGH) |
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d->temp_cmd |= 1 << d->temp_cmd_pos; |
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|
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d->temp_cmd_pos++; |
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|
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if (d->temp_cmd_pos == DS1620_WRITE_SIZE) { |
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switch(d->temp_cmd) { |
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case DS1620_START_CONVT: |
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//printf("temp_sensors: IOS enabled continuous monitoring.\n"); |
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temp_reset(d); |
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break; |
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case DS1620_READ_CONFIG: |
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case DS1620_READ_TEMP: |
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break; |
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default: |
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vm_log(d->router->vm,"IO_FPGA", |
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"temp_sensors: IOS sent command 0x%x.\n", |
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d->temp_cmd); |
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} |
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} |
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} |
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else |
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{ |
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if (val == DS1620_DATA_HIGH) |
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d->temp_data |= 1 << d->temp_data_pos; |
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|
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d->temp_data_pos++; |
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} |
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} |
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|
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/* Console port input */ |
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static void tty_con_input(vtty_t *vtty) |
214 |
{ |
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struct iofpga_data *d = vtty->priv_data; |
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|
217 |
IOFPGA_LOCK(d); |
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if (d->duart_imr & DUART_RXRDYA) { |
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d->duart_isr |= DUART_RXRDYA; |
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vm_set_irq(d->router->vm,C6SUP1_DUART_IRQ); |
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} |
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IOFPGA_UNLOCK(d); |
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} |
224 |
|
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/* AUX port input */ |
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static void tty_aux_input(vtty_t *vtty) |
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{ |
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struct iofpga_data *d = vtty->priv_data; |
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|
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IOFPGA_LOCK(d); |
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if (d->duart_imr & DUART_RXRDYB) { |
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d->duart_isr |= DUART_RXRDYB; |
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vm_set_irq(d->router->vm,C6SUP1_DUART_IRQ); |
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} |
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IOFPGA_UNLOCK(d); |
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} |
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|
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/* IRQ trickery for Console and AUX ports */ |
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static int tty_trigger_dummy_irq(struct iofpga_data *d,void *arg) |
240 |
{ |
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u_int mask; |
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|
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IOFPGA_LOCK(d); |
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d->duart_irq_seq++; |
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|
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if (d->duart_irq_seq == 2) { |
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mask = DUART_TXRDYA|DUART_TXRDYB; |
248 |
if (d->duart_imr & mask) { |
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d->duart_isr |= DUART_TXRDYA|DUART_TXRDYB; |
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vm_set_irq(d->router->vm,C6SUP1_DUART_IRQ); |
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} |
252 |
|
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d->duart_irq_seq = 0; |
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} |
255 |
|
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IOFPGA_UNLOCK(d); |
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return(0); |
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} |
259 |
|
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/* |
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* dev_c6sup1_iofpga_access() |
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*/ |
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void *dev_c6sup1_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
264 |
m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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struct iofpga_data *d = dev->priv_data; |
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vm_instance_t *vm = d->router->vm; |
269 |
u_char odata; |
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|
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if (op_type == MTS_READ) |
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*data = 0x0; |
273 |
|
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#if DEBUG_ACCESS |
275 |
if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx\n", |
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offset,cpu_get_pc(cpu)); |
278 |
} else { |
279 |
cpu_log(cpu,"IO_FPGA","writing reg 0x%x at pc=0x%llx, data=0x%llx\n", |
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offset,cpu_get_pc(cpu),*data); |
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} |
282 |
#endif |
283 |
|
284 |
IOFPGA_LOCK(d); |
285 |
|
286 |
switch(offset) { |
287 |
case 0x294: |
288 |
/* |
289 |
* Unknown, seen in 12.4(6)T, and seems to be read at each |
290 |
* network interrupt. |
291 |
*/ |
292 |
if (op_type == MTS_READ) |
293 |
*data = 0x0; |
294 |
break; |
295 |
|
296 |
/* I/O control register */ |
297 |
case 0x204: |
298 |
if (op_type == MTS_WRITE) { |
299 |
#if DEBUG_IO_CTL |
300 |
vm_log(vm,"IO_FPGA","setting value 0x%llx in io_ctrl_reg\n",*data); |
301 |
#endif |
302 |
d->io_ctrl_reg = *data; |
303 |
} else { |
304 |
*data = d->io_ctrl_reg; |
305 |
*data |= NVRAM_PACKED; /* Packed NVRAM */ |
306 |
} |
307 |
break; |
308 |
|
309 |
/* Watchdog */ |
310 |
case 0x234: |
311 |
break; |
312 |
|
313 |
/* |
314 |
* FPGA release/presence ? Flash SIMM size: |
315 |
* 0x0001: 2048K Flash (2 banks) |
316 |
* 0x0504: 8192K Flash (2 banks) |
317 |
* 0x0704: 16384K Flash (2 banks) |
318 |
* 0x0904: 32768K Flash (2 banks) |
319 |
* 0x0B04: 65536K Flash (2 banks) |
320 |
* 0x2001: 1024K Flash (1 bank) |
321 |
* 0x2504: 4096K Flash (1 bank) |
322 |
* 0x2704: 8192K Flash (1 bank) |
323 |
* 0x2904: 16384K Flash (1 bank) |
324 |
* 0x2B04: 32768K Flash (1 bank) |
325 |
* |
326 |
* Number of Flash SIMM banks + size. |
327 |
* Touching some lower bits causes problems with environmental monitor. |
328 |
* |
329 |
* It is displayed by command "sh bootflash: chips" |
330 |
*/ |
331 |
case 0x23c: |
332 |
if (op_type == MTS_READ) |
333 |
*data = 0x2704; |
334 |
break; |
335 |
|
336 |
/* LEDs */ |
337 |
case 0x244: |
338 |
#if DEBUG_LED |
339 |
vm_log(vm,"IO_FPGA","LED register is now 0x%x (0x%x)\n", |
340 |
*data,(~*data) & 0x0F); |
341 |
#endif |
342 |
break; |
343 |
|
344 |
/* ==== DUART SCN2681 (console/aux) ==== */ |
345 |
case 0x404: /* Mode Register A (MRA) */ |
346 |
break; |
347 |
|
348 |
case 0x40c: /* Status Register A (SRA) */ |
349 |
if (op_type == MTS_READ) { |
350 |
odata = 0; |
351 |
|
352 |
if (vtty_is_char_avail(vm->vtty_con)) |
353 |
odata |= DUART_RX_READY; |
354 |
|
355 |
odata |= DUART_TX_READY; |
356 |
|
357 |
vm_clear_irq(vm,C6SUP1_DUART_IRQ); |
358 |
*data = odata; |
359 |
} |
360 |
break; |
361 |
|
362 |
case 0x414: /* Command Register A (CRA) */ |
363 |
/* Disable TX = High */ |
364 |
if ((op_type == MTS_WRITE) && (*data & 0x8)) { |
365 |
vm->vtty_con->managed_flush = TRUE; |
366 |
vtty_flush(vm->vtty_con); |
367 |
} |
368 |
break; |
369 |
|
370 |
case 0x41c: /* RX/TX Holding Register A (RHRA/THRA) */ |
371 |
if (op_type == MTS_WRITE) { |
372 |
vtty_put_char(vm->vtty_con,(char)*data); |
373 |
d->duart_isr &= ~DUART_TXRDYA; |
374 |
} else { |
375 |
*data = vtty_get_char(vm->vtty_con); |
376 |
d->duart_isr &= ~DUART_RXRDYA; |
377 |
} |
378 |
break; |
379 |
|
380 |
case 0x424: /* WRITE: Aux Control Register (ACR) */ |
381 |
break; |
382 |
|
383 |
case 0x42c: /* Interrupt Status/Mask Register (ISR/IMR) */ |
384 |
if (op_type == MTS_WRITE) { |
385 |
d->duart_imr = *data; |
386 |
} else |
387 |
*data = d->duart_isr; |
388 |
break; |
389 |
|
390 |
case 0x434: /* Counter/Timer Upper Value (CTU) */ |
391 |
case 0x43c: /* Counter/Timer Lower Value (CTL) */ |
392 |
case 0x444: /* Mode Register B (MRB) */ |
393 |
break; |
394 |
|
395 |
case 0x44c: /* Status Register B (SRB) */ |
396 |
if (op_type == MTS_READ) { |
397 |
odata = 0; |
398 |
|
399 |
if (vtty_is_char_avail(vm->vtty_aux)) |
400 |
odata |= DUART_RX_READY; |
401 |
|
402 |
odata |= DUART_TX_READY; |
403 |
|
404 |
//vm_clear_irq(vm,C6SUP1_DUART_IRQ); |
405 |
*data = odata; |
406 |
} |
407 |
break; |
408 |
|
409 |
case 0x454: /* Command Register B (CRB) */ |
410 |
/* Disable TX = High */ |
411 |
if ((op_type == MTS_WRITE) && (*data & 0x8)) { |
412 |
vm->vtty_aux->managed_flush = TRUE; |
413 |
vtty_flush(vm->vtty_aux); |
414 |
} |
415 |
break; |
416 |
|
417 |
case 0x45c: /* RX/TX Holding Register B (RHRB/THRB) */ |
418 |
if (op_type == MTS_WRITE) { |
419 |
vtty_put_char(vm->vtty_aux,(char)*data); |
420 |
d->duart_isr &= ~DUART_TXRDYA; |
421 |
} else { |
422 |
*data = vtty_get_char(vm->vtty_aux); |
423 |
d->duart_isr &= ~DUART_RXRDYB; |
424 |
} |
425 |
break; |
426 |
|
427 |
case 0x46c: /* WRITE: Output Port Configuration Register (OPCR) */ |
428 |
case 0x474: /* READ: Start Counter Command; */ |
429 |
/* WRITE: Set Output Port Bits Command */ |
430 |
case 0x47c: /* WRITE: Reset Output Port Bits Command */ |
431 |
break; |
432 |
|
433 |
/* ==== DS 1620 (temp sensors) ==== */ |
434 |
case 0x20c: /* Temperature Control */ |
435 |
if (op_type == MTS_WRITE) |
436 |
temp_write_ctrl(d,*data); |
437 |
break; |
438 |
|
439 |
case 0x214: /* Temperature data write */ |
440 |
if (op_type == MTS_WRITE) { |
441 |
temp_write_data(d,*data); |
442 |
d->mux = *data; |
443 |
} |
444 |
break; |
445 |
|
446 |
case 0x22c: /* Temperature data read */ |
447 |
if (op_type == MTS_READ) |
448 |
*data = temp_read_data(d); |
449 |
break; |
450 |
|
451 |
#if DEBUG_UNKNOWN |
452 |
default: |
453 |
if (op_type == MTS_READ) { |
454 |
cpu_log(cpu,"IO_FPGA","read from addr 0x%x, pc=0x%llx (size=%u)\n", |
455 |
offset,cpu_get_pc(cpu),op_size); |
456 |
} else { |
457 |
cpu_log(cpu,"IO_FPGA","write to addr 0x%x, value=0x%llx, " |
458 |
"pc=0x%llx (size=%u)\n", |
459 |
offset,*data,cpu_get_pc(cpu),op_size); |
460 |
} |
461 |
#endif |
462 |
} |
463 |
|
464 |
IOFPGA_UNLOCK(d); |
465 |
return NULL; |
466 |
} |
467 |
|
468 |
/* Shutdown the IO FPGA device */ |
469 |
void dev_c6sup1_iofpga_shutdown(vm_instance_t *vm,struct iofpga_data *d) |
470 |
{ |
471 |
if (d != NULL) { |
472 |
IOFPGA_LOCK(d); |
473 |
vm->vtty_con->read_notifier = NULL; |
474 |
vm->vtty_aux->read_notifier = NULL; |
475 |
IOFPGA_UNLOCK(d); |
476 |
|
477 |
/* Remove the dummy IRQ periodic task */ |
478 |
ptask_remove(d->duart_irq_tid); |
479 |
|
480 |
/* Remove the device */ |
481 |
dev_remove(vm,&d->dev); |
482 |
|
483 |
/* Free the structure itself */ |
484 |
free(d); |
485 |
} |
486 |
} |
487 |
|
488 |
/* |
489 |
* dev_c6sup1_iofpga_init() |
490 |
*/ |
491 |
int dev_c6sup1_iofpga_init(c6sup1_t *router,m_uint64_t paddr,m_uint32_t len) |
492 |
{ |
493 |
vm_instance_t *vm = router->vm; |
494 |
struct iofpga_data *d; |
495 |
u_int i; |
496 |
|
497 |
/* Allocate private data structure */ |
498 |
if (!(d = malloc(sizeof(*d)))) { |
499 |
fprintf(stderr,"IO_FPGA: out of memory\n"); |
500 |
return(-1); |
501 |
} |
502 |
|
503 |
memset(d,0,sizeof(*d)); |
504 |
|
505 |
pthread_mutex_init(&d->lock,NULL); |
506 |
d->router = router; |
507 |
|
508 |
for(i=0;i<C6SUP1_TEMP_SENSORS;i++) { |
509 |
d->temp_cfg_reg[i] = DS1620_CONFIG_STATUS_CPU; |
510 |
d->temp_deg_reg[i] = C6SUP1_DEFAULT_TEMP * 2; |
511 |
} |
512 |
|
513 |
vm_object_init(&d->vm_obj); |
514 |
d->vm_obj.name = "io_fpga"; |
515 |
d->vm_obj.data = d; |
516 |
d->vm_obj.shutdown = (vm_shutdown_t)dev_c6sup1_iofpga_shutdown; |
517 |
|
518 |
/* Set device properties */ |
519 |
dev_init(&d->dev); |
520 |
d->dev.name = "io_fpga"; |
521 |
d->dev.phys_addr = paddr; |
522 |
d->dev.phys_len = len; |
523 |
d->dev.handler = dev_c6sup1_iofpga_access; |
524 |
d->dev.priv_data = d; |
525 |
|
526 |
/* Set console and AUX port notifying functions */ |
527 |
vm->vtty_con->priv_data = d; |
528 |
vm->vtty_aux->priv_data = d; |
529 |
vm->vtty_con->read_notifier = tty_con_input; |
530 |
vm->vtty_aux->read_notifier = tty_aux_input; |
531 |
|
532 |
/* Trigger periodically a dummy IRQ to flush buffers */ |
533 |
d->duart_irq_tid = ptask_add((ptask_callback)tty_trigger_dummy_irq, |
534 |
d,NULL); |
535 |
|
536 |
/* Map this device to the VM */ |
537 |
vm_bind_device(vm,&d->dev); |
538 |
vm_object_add(vm,&d->vm_obj); |
539 |
return(0); |
540 |
} |