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dpavlin |
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/* |
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* Cisco 3745 simulation platform. |
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* Copyright (c) 2006 Christophe Fillot (cf@utc.fr) |
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*/ |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <unistd.h> |
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#include <sys/types.h> |
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#include <termios.h> |
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#include <fcntl.h> |
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#include <pthread.h> |
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#include "ptask.h" |
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dpavlin |
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#include "cpu.h" |
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#include "vm.h" |
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dpavlin |
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#include "dynamips.h" |
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#include "memory.h" |
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#include "device.h" |
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#include "dev_vtty.h" |
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dpavlin |
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#include "nmc93cX6.h" |
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dpavlin |
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#include "dev_c3745.h" |
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/* Debugging flags */ |
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#define DEBUG_UNKNOWN 1 |
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#define DEBUG_ACCESS 0 |
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dpavlin |
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#define DEBUG_NET_IRQ 0 |
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dpavlin |
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/* Definitions for Motherboard EEPROM (0x00) */ |
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#define EEPROM_MB_DOUT 3 |
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#define EEPROM_MB_DIN 2 |
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#define EEPROM_MB_CLK 1 |
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#define EEPROM_MB_CS 0 |
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/* Definitions for I/O board EEPROM (0x01) */ |
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#define EEPROM_IO_DOUT 3 |
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#define EEPROM_IO_DIN 2 |
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#define EEPROM_IO_CLK 1 |
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#define EEPROM_IO_CS 8 |
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/* Definitions for Midplane EEPROM (0x02) */ |
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#define EEPROM_MP_DOUT 3 |
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#define EEPROM_MP_DIN 2 |
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#define EEPROM_MP_CLK 1 |
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#define EEPROM_MP_CS 9 |
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/* Definitions for Network Modules EEPROM */ |
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#define EEPROM_NM_DOUT 7 |
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#define EEPROM_NM_DIN 6 |
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#define EEPROM_NM_CLK 2 |
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#define EEPROM_NM_CS 4 |
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dpavlin |
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/* Network IRQ distribution */ |
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struct net_irq_distrib { |
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u_int reg; |
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u_int offset; |
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}; |
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dpavlin |
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dpavlin |
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static struct net_irq_distrib net_irq_dist[C3745_MAX_NM_BAYS] = { |
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{ 0, 0 }, /* Slot 0: reg 0x20, 0x00XX */ |
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{ 1, 0 }, /* Slot 1: reg 0x22, 0x000X */ |
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{ 1, 4 }, /* Slot 2: reg 0x22, 0x00X0 */ |
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{ 1, 8 }, /* Slot 3: reg 0x22, 0x0X00 */ |
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{ 1, 12 }, /* Slot 4: reg 0x22, 0xX000 */ |
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}; |
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dpavlin |
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/* IO FPGA structure */ |
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dpavlin |
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struct c3745_iofpga_data { |
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dpavlin |
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vm_obj_t vm_obj; |
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struct vdevice dev; |
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c3745_t *router; |
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dpavlin |
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/* Network IRQ status */ |
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m_uint16_t net_irq_status[2]; |
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dpavlin |
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/* Interrupt mask */ |
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m_uint16_t intr_mask,io_mask2; |
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/* EEPROM select */ |
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u_int eeprom_select; |
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dpavlin |
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/* WIC select */ |
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u_int wic_select; |
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u_int wic_cmd_pos; |
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u_int wic_cmd_valid; |
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m_uint16_t wic_cmd[2]; |
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dpavlin |
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}; |
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/* Motherboard EEPROM definition */ |
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dpavlin |
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static const struct nmc93cX6_eeprom_def eeprom_mb_def = { |
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dpavlin |
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EEPROM_MB_CLK, EEPROM_MB_CS, |
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EEPROM_MB_DIN, EEPROM_MB_DOUT, |
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}; |
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/* I/O board EEPROM definition */ |
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dpavlin |
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static const struct nmc93cX6_eeprom_def eeprom_io_def = { |
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dpavlin |
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EEPROM_IO_CLK, EEPROM_IO_CS, |
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EEPROM_IO_DIN, EEPROM_IO_DOUT, |
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}; |
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/* Midplane EEPROM definition */ |
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dpavlin |
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static const struct nmc93cX6_eeprom_def eeprom_mp_def = { |
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dpavlin |
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EEPROM_MP_CLK, EEPROM_MP_CS, |
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EEPROM_MP_DIN, EEPROM_MP_DOUT, |
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}; |
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/* System EEPROM group */ |
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dpavlin |
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static const struct nmc93cX6_group eeprom_sys_group = { |
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dpavlin |
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EEPROM_TYPE_NMC93C46, 3, 0, |
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EEPROM_DORD_NORMAL, |
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EEPROM_DOUT_HIGH, |
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EEPROM_DEBUG_DISABLED, |
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"System EEPROM", |
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dpavlin |
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{ &eeprom_mb_def, &eeprom_io_def, &eeprom_mp_def }, |
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}; |
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/* NM EEPROM definition */ |
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dpavlin |
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static const struct nmc93cX6_eeprom_def eeprom_nm_def = { |
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dpavlin |
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EEPROM_NM_CLK, EEPROM_NM_CS, |
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EEPROM_NM_DIN, EEPROM_NM_DOUT, |
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}; |
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/* NM EEPROM */ |
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dpavlin |
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static const struct nmc93cX6_group eeprom_nm_group = { |
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dpavlin |
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EEPROM_TYPE_NMC93C46, 1, 0, |
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EEPROM_DORD_NORMAL, |
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EEPROM_DOUT_HIGH, |
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EEPROM_DEBUG_DISABLED, |
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"NM EEPROM", |
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{ &eeprom_nm_def }, |
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dpavlin |
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}; |
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dpavlin |
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/* Update network interrupt status */ |
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static inline void dev_c3745_iofpga_net_update_irq(struct c3745_iofpga_data *d) |
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{ |
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if ((d->net_irq_status[0] != 0xFFFF) || (d->net_irq_status[1] != 0xFFFF)) { |
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vm_set_irq(d->router->vm,C3745_NETIO_IRQ); |
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} else { |
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vm_clear_irq(d->router->vm,C3745_NETIO_IRQ); |
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} |
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} |
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/* Trigger a Network IRQ for the specified slot/port */ |
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void dev_c3745_iofpga_net_set_irq(struct c3745_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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struct net_irq_distrib *irq_dist; |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","setting NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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irq_dist = &net_irq_dist[slot]; |
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d->net_irq_status[irq_dist->reg] &= ~(1 << (irq_dist->offset + port)); |
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dev_c3745_iofpga_net_update_irq(d); |
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} |
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/* Clear a Network IRQ for the specified slot/port */ |
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void dev_c3745_iofpga_net_clear_irq(struct c3745_iofpga_data *d, |
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u_int slot,u_int port) |
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{ |
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struct net_irq_distrib *irq_dist; |
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#if DEBUG_NET_IRQ |
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vm_log(d->router->vm,"IO_FPGA","clearing NetIRQ for slot %u port %u\n", |
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slot,port); |
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#endif |
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irq_dist = &net_irq_dist[slot]; |
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d->net_irq_status[irq_dist->reg] |= (1 << (irq_dist->offset + port)); |
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dev_c3745_iofpga_net_update_irq(d); |
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} |
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dpavlin |
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/* Read a WIC EEPROM */ |
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static m_uint16_t dev_c3745_read_wic_eeprom(struct c3745_iofpga_data *d) |
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{ |
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struct cisco_eeprom *eeprom; |
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u_int wic_port; |
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u_int eeprom_offset; |
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m_uint8_t val[2]; |
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switch(d->wic_select) { |
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case 0x1700: |
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wic_port = 0x10; |
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break; |
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case 0x1D00: |
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wic_port = 0x20; |
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break; |
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case 0x3500: |
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wic_port = 0x30; |
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break; |
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default: |
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wic_port = 0; |
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} |
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/* No WIC in slot or no EEPROM: fake an empty EEPROM */ |
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if (!wic_port || !(eeprom = vm_slot_get_eeprom(d->router->vm,0,wic_port))) |
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return(0xFFFF); |
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/* EEPROM offset is in the lowest 6 bits */ |
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eeprom_offset = d->wic_cmd[0] & 0x3F; |
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cisco_eeprom_get_byte(eeprom,eeprom_offset,&val[0]); |
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cisco_eeprom_get_byte(eeprom,eeprom_offset+1,&val[1]); |
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return(((m_uint16_t)val[0] << 8) | val[1]); |
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} |
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dpavlin |
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/* |
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* dev_c3745_iofpga_access() |
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*/ |
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static void * |
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dpavlin |
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dev_c3745_iofpga_access(cpu_gen_t *cpu,struct vdevice *dev, |
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dpavlin |
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m_uint32_t offset,u_int op_size,u_int op_type, |
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m_uint64_t *data) |
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{ |
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dpavlin |
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struct c3745_iofpga_data *d = dev->priv_data; |
218 |
dpavlin |
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u_int slot; |
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220 |
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if (op_type == MTS_READ) |
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*data = 0x0; |
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dpavlin |
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dpavlin |
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#if DEBUG_ACCESS |
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if (op_type == MTS_READ) { |
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cpu_log(cpu,"IO_FPGA","reading reg 0x%x at pc=0x%llx (size=%u)\n", |
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dpavlin |
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offset,cpu_get_pc(cpu),op_size); |
227 |
dpavlin |
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} else { |
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cpu_log(cpu,"IO_FPGA", |
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"writing reg 0x%x at pc=0x%llx, data=0x%llx (size=%u)\n", |
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dpavlin |
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offset,cpu_get_pc(cpu),*data,op_size); |
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dpavlin |
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} |
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#endif |
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switch(offset) { |
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/* Unknown */ |
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case 0x000000: |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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241 |
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/* Unknown */ |
242 |
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case 0x000004: |
243 |
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if (op_type == MTS_READ) |
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*data = 0xFFFF; |
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break; |
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247 |
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/* |
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* CompactFlash. |
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* |
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* Bit 0: Slot0 Compact Flash presence. |
251 |
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* Bit 1: System Compact Flash presence. |
252 |
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*/ |
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case 0x000012: |
254 |
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if (op_type == MTS_READ) { |
255 |
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*data = 0xFFFF; |
256 |
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257 |
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/* System Flash ? */ |
258 |
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if (cpu->vm->pcmcia_disk_size[0]) |
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*data &= ~0x02; |
260 |
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261 |
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/* Slot0 Flash ? */ |
262 |
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if (cpu->vm->pcmcia_disk_size[1]) |
263 |
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*data &= ~0x01; |
264 |
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} |
265 |
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break; |
266 |
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267 |
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/* Suppress the "****TDM FPGA download failed.." message */ |
268 |
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case 0x000014: |
269 |
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if (op_type == MTS_READ) |
270 |
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*data = 0x00FF; |
271 |
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break; |
272 |
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273 |
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/* Power supply status */ |
274 |
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case 0x00000a: |
275 |
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if (op_type == MTS_READ) |
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*data = 0x0000; |
277 |
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break; |
278 |
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279 |
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/* Fan status */ |
280 |
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case 0x00000c: |
281 |
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if (op_type == MTS_READ) |
282 |
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*data = 0x0000; |
283 |
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break; |
284 |
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285 |
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/* System EEPROMs */ |
286 |
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case 0x00000e: |
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if (op_type == MTS_WRITE) |
288 |
dpavlin |
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nmc93cX6_write(&d->router->sys_eeprom_group,(u_int)(*data)); |
289 |
dpavlin |
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else |
290 |
dpavlin |
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*data = nmc93cX6_read(&d->router->sys_eeprom_group); |
291 |
dpavlin |
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break; |
292 |
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293 |
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/* |
294 |
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* Network interrupt status. |
295 |
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* |
296 |
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* Bit 0: 0 = GT96100 Ethernet ports. |
297 |
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* Bit 8: 0 = AIM slot 0. |
298 |
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* Bit 9: 0 = AIM slot 1. |
299 |
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*/ |
300 |
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case 0x000020: |
301 |
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if (op_type == MTS_READ) |
302 |
dpavlin |
8 |
*data = d->net_irq_status[0]; |
303 |
dpavlin |
4 |
break; |
304 |
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305 |
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/* |
306 |
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* Network interrupt status. |
307 |
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* |
308 |
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* Bit 0: 0 = Interrupt for slot 1 |
309 |
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* Bit 4: 0 = Interrupt for slot 2 |
310 |
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* Bit 8: 0 = Interrupt for slot 3 |
311 |
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* Bit 12: 0 = Interrupt for slot 4 |
312 |
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*/ |
313 |
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case 0x000022: |
314 |
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if (op_type == MTS_READ) |
315 |
dpavlin |
8 |
*data = d->net_irq_status[1]; |
316 |
dpavlin |
4 |
break; |
317 |
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318 |
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/* |
319 |
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* Per Slot Intr Mask (seen with "sh platform"). |
320 |
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* IO Mask 1 is the lower 8-bits. |
321 |
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*/ |
322 |
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case 0x00002a: |
323 |
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if (op_type == MTS_READ) |
324 |
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*data = d->intr_mask; |
325 |
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else |
326 |
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d->intr_mask = *data; |
327 |
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break; |
328 |
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329 |
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/* IO Mask 2 (seen with "sh platform") */ |
330 |
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case 0x00002c: |
331 |
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if (op_type == MTS_READ) |
332 |
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*data = d->io_mask2; |
333 |
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else |
334 |
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d->io_mask2 = *data; |
335 |
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break; |
336 |
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337 |
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/* EEPROM in slots 1-4 */ |
338 |
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case 0x000040: |
339 |
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case 0x000042: |
340 |
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case 0x000044: |
341 |
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case 0x000046: |
342 |
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slot = (offset - 0x000040) >> 1; |
343 |
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344 |
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if (op_type == MTS_WRITE) |
345 |
dpavlin |
8 |
nmc93cX6_write(&d->router->nm_eeprom_group[slot],(u_int)(*data)); |
346 |
dpavlin |
4 |
else |
347 |
dpavlin |
8 |
*data = nmc93cX6_read(&d->router->nm_eeprom_group[slot]); |
348 |
dpavlin |
4 |
break; |
349 |
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350 |
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/* AIM slot 0 EEPROM */ |
351 |
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case 0x000048: |
352 |
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if (op_type == MTS_READ) |
353 |
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*data = 0xFFFF; |
354 |
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break; |
355 |
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356 |
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/* AIM slot 1 EEPROM */ |
357 |
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case 0x00004A: |
358 |
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if (op_type == MTS_READ) |
359 |
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*data = 0xFFFF; |
360 |
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break; |
361 |
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362 |
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/* |
363 |
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* NM presence. |
364 |
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* |
365 |
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* Bit 0: 0 = NM present in slot 2 (0x42) |
366 |
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* Bit 4: 0 = NM present in slot 4 (0x46) |
367 |
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* Bit 8: 0 = NM present in slot 1 (0x40) |
368 |
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* Bit 12: 0 = NM present in slot 3 (0x44) |
369 |
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*/ |
370 |
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case 0x00004e: |
371 |
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if (op_type == MTS_READ) { |
372 |
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*data = 0xFFFF; |
373 |
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|
374 |
dpavlin |
11 |
if (vm_slot_get_card_ptr(d->router->vm,1)) |
375 |
dpavlin |
4 |
*data &= ~0x0100; |
376 |
|
|
|
377 |
dpavlin |
11 |
if (vm_slot_get_card_ptr(d->router->vm,2)) |
378 |
dpavlin |
4 |
*data &= ~0x0001; |
379 |
|
|
|
380 |
dpavlin |
11 |
if (vm_slot_get_card_ptr(d->router->vm,3)) |
381 |
dpavlin |
4 |
*data &= ~0x1000; |
382 |
|
|
|
383 |
dpavlin |
11 |
if (vm_slot_get_card_ptr(d->router->vm,4)) |
384 |
dpavlin |
4 |
*data &= ~0x0010; |
385 |
|
|
} |
386 |
|
|
break; |
387 |
|
|
|
388 |
dpavlin |
11 |
/* |
389 |
|
|
* VWIC/WIC related |
390 |
|
|
* Bits 0-2: WIC presence |
391 |
|
|
*/ |
392 |
dpavlin |
4 |
case 0x100004: |
393 |
dpavlin |
11 |
if (op_type == MTS_READ) { |
394 |
|
|
*data = 0xFFFF; |
395 |
|
|
|
396 |
|
|
/* check WIC 0 */ |
397 |
|
|
if (vm_slot_check_eeprom(d->router->vm,0,0x10)) |
398 |
|
|
*data &= ~0x01; |
399 |
|
|
|
400 |
|
|
/* check WIC 1 */ |
401 |
|
|
if (vm_slot_check_eeprom(d->router->vm,0,0x20)) |
402 |
|
|
*data &= ~0x02; |
403 |
|
|
|
404 |
|
|
/* check WIC 2 */ |
405 |
|
|
if (vm_slot_check_eeprom(d->router->vm,0,0x30)) |
406 |
|
|
*data &= ~0x04; |
407 |
|
|
} else { |
408 |
|
|
d->wic_select = *data; |
409 |
|
|
} |
410 |
|
|
break; |
411 |
|
|
|
412 |
dpavlin |
4 |
case 0x100006: |
413 |
|
|
if (op_type == MTS_READ) |
414 |
dpavlin |
11 |
*data = 0x0004; |
415 |
dpavlin |
4 |
break; |
416 |
|
|
|
417 |
dpavlin |
11 |
case 0x100008: |
418 |
|
|
if (op_type == MTS_READ) { |
419 |
|
|
if (d->wic_cmd_valid) { |
420 |
|
|
*data = dev_c3745_read_wic_eeprom(d); |
421 |
|
|
d->wic_cmd_valid = FALSE; |
422 |
|
|
} else { |
423 |
|
|
*data = 0xFFFF; |
424 |
|
|
} |
425 |
|
|
} else { |
426 |
|
|
/* |
427 |
|
|
* Store the EEPROM command (in 2 words). |
428 |
|
|
* |
429 |
|
|
* For a read, we have: |
430 |
|
|
* Word 0: 0x180 (nmc93c46 READ) + offset (6-bits). |
431 |
|
|
* Word 1: 0 (no data). |
432 |
|
|
*/ |
433 |
|
|
d->wic_cmd[d->wic_cmd_pos++] = *data; |
434 |
|
|
|
435 |
|
|
if (d->wic_cmd_pos == 2) { |
436 |
|
|
d->wic_cmd_pos = 0; |
437 |
|
|
d->wic_cmd_valid = TRUE; |
438 |
|
|
} |
439 |
|
|
} |
440 |
|
|
break; |
441 |
|
|
|
442 |
dpavlin |
4 |
#if DEBUG_UNKNOWN |
443 |
|
|
default: |
444 |
|
|
if (op_type == MTS_READ) { |
445 |
|
|
cpu_log(cpu,"IO_FPGA", |
446 |
|
|
"read from unknown addr 0x%x, pc=0x%llx (size=%u)\n", |
447 |
dpavlin |
7 |
offset,cpu_get_pc(cpu),op_size); |
448 |
dpavlin |
4 |
} else { |
449 |
|
|
cpu_log(cpu,"IO_FPGA", |
450 |
|
|
"write to unknown addr 0x%x, value=0x%llx, " |
451 |
dpavlin |
7 |
"pc=0x%llx (size=%u)\n", |
452 |
|
|
offset,*data,cpu_get_pc(cpu),op_size); |
453 |
dpavlin |
4 |
} |
454 |
|
|
#endif |
455 |
|
|
} |
456 |
|
|
|
457 |
|
|
return NULL; |
458 |
|
|
} |
459 |
|
|
|
460 |
|
|
/* Initialize EEPROM groups */ |
461 |
|
|
void c3745_init_eeprom_groups(c3745_t *router) |
462 |
|
|
{ |
463 |
|
|
int i; |
464 |
|
|
|
465 |
|
|
/* Initialize Mainboard EEPROM */ |
466 |
|
|
router->sys_eeprom_group = eeprom_sys_group; |
467 |
|
|
|
468 |
|
|
for(i=0;i<3;i++) { |
469 |
|
|
router->sys_eeprom_group.eeprom[i] = &router->sys_eeprom[i]; |
470 |
|
|
router->sys_eeprom[i].data = NULL; |
471 |
|
|
router->sys_eeprom[i].len = 0; |
472 |
|
|
} |
473 |
|
|
|
474 |
|
|
/* EEPROMs for Network Modules */ |
475 |
|
|
for(i=1;i<=4;i++) { |
476 |
|
|
router->nm_eeprom_group[i-1] = eeprom_nm_group; |
477 |
dpavlin |
11 |
router->nm_eeprom_group[i-1].eeprom[0] = NULL; |
478 |
dpavlin |
4 |
} |
479 |
|
|
} |
480 |
|
|
|
481 |
|
|
/* Shutdown the IO FPGA device */ |
482 |
dpavlin |
8 |
static void |
483 |
|
|
dev_c3745_iofpga_shutdown(vm_instance_t *vm,struct c3745_iofpga_data *d) |
484 |
dpavlin |
4 |
{ |
485 |
|
|
if (d != NULL) { |
486 |
|
|
/* Remove the device */ |
487 |
|
|
dev_remove(vm,&d->dev); |
488 |
|
|
|
489 |
|
|
/* Free the structure itself */ |
490 |
|
|
free(d); |
491 |
|
|
} |
492 |
|
|
} |
493 |
|
|
|
494 |
|
|
/* |
495 |
|
|
* dev_c3745_iofpga_init() |
496 |
|
|
*/ |
497 |
|
|
int dev_c3745_iofpga_init(c3745_t *router,m_uint64_t paddr,m_uint32_t len) |
498 |
|
|
{ |
499 |
|
|
vm_instance_t *vm = router->vm; |
500 |
dpavlin |
8 |
struct c3745_iofpga_data *d; |
501 |
dpavlin |
4 |
|
502 |
|
|
/* Allocate private data structure */ |
503 |
|
|
if (!(d = malloc(sizeof(*d)))) { |
504 |
|
|
fprintf(stderr,"IO_FPGA: out of memory\n"); |
505 |
|
|
return(-1); |
506 |
|
|
} |
507 |
|
|
|
508 |
|
|
memset(d,0,sizeof(*d)); |
509 |
|
|
d->router = router; |
510 |
dpavlin |
8 |
d->net_irq_status[0] = 0xFFFF; |
511 |
|
|
d->net_irq_status[1] = 0xFFFF; |
512 |
dpavlin |
4 |
|
513 |
|
|
vm_object_init(&d->vm_obj); |
514 |
|
|
d->vm_obj.name = "io_fpga"; |
515 |
|
|
d->vm_obj.data = d; |
516 |
|
|
d->vm_obj.shutdown = (vm_shutdown_t)dev_c3745_iofpga_shutdown; |
517 |
|
|
|
518 |
|
|
/* Set device properties */ |
519 |
|
|
dev_init(&d->dev); |
520 |
|
|
d->dev.name = "io_fpga"; |
521 |
|
|
d->dev.phys_addr = paddr; |
522 |
|
|
d->dev.phys_len = len; |
523 |
|
|
d->dev.priv_data = d; |
524 |
|
|
d->dev.handler = dev_c3745_iofpga_access; |
525 |
|
|
|
526 |
|
|
/* Map this device to the VM */ |
527 |
|
|
vm_bind_device(router->vm,&d->dev); |
528 |
|
|
vm_object_add(vm,&d->vm_obj); |
529 |
|
|
return(0); |
530 |
|
|
} |