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/* |
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* Cisco router simulation platform. |
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* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr) |
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*/ |
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#ifndef __CPU_H__ |
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#define __CPU_H__ |
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#include <pthread.h> |
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#include <setjmp.h> |
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#include "utils.h" |
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#include "jit_op.h" |
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#include "mips64.h" |
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#include "mips64_cp0.h" |
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#include "ppc32.h" |
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/* Possible CPU types */ |
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enum { |
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CPU_TYPE_MIPS64 = 1, |
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CPU_TYPE_PPC32, |
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}; |
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/* Virtual CPU states */ |
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enum { |
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CPU_STATE_RUNNING = 0, |
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CPU_STATE_HALTED, |
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CPU_STATE_SUSPENDED, |
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}; |
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/* Maximum results for idle pc */ |
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#define CPU_IDLE_PC_MAX_RES 10 |
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/* Idle PC proposed value */ |
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struct cpu_idle_pc { |
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m_uint64_t pc; |
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u_int count; |
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}; |
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/* Number of recorded memory accesses (power of two) */ |
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#define MEMLOG_COUNT 16 |
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typedef struct memlog_access memlog_access_t; |
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struct memlog_access { |
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m_uint64_t iaddr; |
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m_uint64_t vaddr; |
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m_uint64_t data; |
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m_uint32_t data_valid; |
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m_uint32_t op_size; |
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m_uint32_t op_type; |
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}; |
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/* Undefined memory access handler */ |
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typedef int (*cpu_undefined_mem_handler_t)(cpu_gen_t *cpu,m_uint64_t vaddr, |
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u_int op_size,u_int op_type, |
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m_uint64_t *data); |
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/* Generic CPU definition */ |
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struct cpu_gen { |
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/* CPU type and identifier for MP systems */ |
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u_int type,id; |
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/* CPU states */ |
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volatile u_int state,prev_state; |
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volatile m_uint64_t seq_state; |
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/* Thread running this CPU */ |
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pthread_t cpu_thread; |
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int cpu_thread_running; |
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/* Exception restore point */ |
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jmp_buf exec_loop_env; |
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/* "Idle" loop management */ |
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u_int idle_count,idle_max,idle_sleep_time; |
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pthread_mutex_t idle_mutex; |
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pthread_cond_t idle_cond; |
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/* VM instance */ |
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vm_instance_t *vm; |
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/* Next CPU in group */ |
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cpu_gen_t *next; |
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/* Idle PC proposal */ |
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struct cpu_idle_pc idle_pc_prop[CPU_IDLE_PC_MAX_RES]; |
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u_int idle_pc_prop_count; |
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/* Specific CPU part */ |
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union { |
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cpu_mips_t mips64_cpu; |
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cpu_ppc_t ppc32_cpu; |
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}sp; |
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/* Methods */ |
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void (*reg_set)(cpu_gen_t *cpu,u_int reg_index,m_uint64_t val); |
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void (*reg_dump)(cpu_gen_t *cpu); |
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void (*mmu_dump)(cpu_gen_t *cpu); |
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void (*mmu_raw_dump)(cpu_gen_t *cpu); |
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void (*add_breakpoint)(cpu_gen_t *cpu,m_uint64_t addr); |
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void (*remove_breakpoint)(cpu_gen_t *cpu,m_uint64_t addr); |
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void (*set_idle_pc)(cpu_gen_t *cpu,m_uint64_t addr); |
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void (*get_idling_pc)(cpu_gen_t *cpu); |
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void (*mts_rebuild)(cpu_gen_t *cpu); |
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void (*mts_show_stats)(cpu_gen_t *cpu); |
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cpu_undefined_mem_handler_t undef_mem_handler; |
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/* Memory access log for fault debugging */ |
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u_int memlog_pos; |
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memlog_access_t memlog_array[MEMLOG_COUNT]; |
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/* Statistics */ |
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m_uint64_t dev_access_counter; |
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/* JIT op array for current compiled page */ |
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u_int jit_op_array_size; |
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jit_op_t **jit_op_array; |
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jit_op_t **jit_op_current; |
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/* JIT op pool */ |
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jit_op_t *jit_op_pool[JIT_OP_POOL_NR]; |
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}; |
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/* CPU group definition */ |
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typedef struct cpu_group cpu_group_t; |
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struct cpu_group { |
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char *name; |
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cpu_gen_t *cpu_list; |
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void *priv_data; |
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}; |
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#define CPU_MIPS64(cpu) (&(cpu)->sp.mips64_cpu) |
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#define CPU_PPC32(cpu) (&(cpu)->sp.ppc32_cpu) |
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/* Get CPU instruction pointer */ |
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static forced_inline m_uint64_t cpu_get_pc(cpu_gen_t *cpu) |
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{ |
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switch(cpu->type) { |
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case CPU_TYPE_MIPS64: |
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return(CPU_MIPS64(cpu)->pc); |
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case CPU_TYPE_PPC32: |
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return((m_uint64_t)CPU_PPC32(cpu)->ia); |
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default: |
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return(0); |
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} |
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} |
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/* Get CPU performance counter */ |
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static forced_inline m_uint32_t cpu_get_perf_counter(cpu_gen_t *cpu) |
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{ |
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switch(cpu->type) { |
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case CPU_TYPE_MIPS64: |
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return(CPU_MIPS64(cpu)->perf_counter); |
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case CPU_TYPE_PPC32: |
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return(CPU_PPC32(cpu)->perf_counter); |
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default: |
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return(0); |
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} |
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} |
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/* Find a CPU in a group given its ID */ |
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cpu_gen_t *cpu_group_find_id(cpu_group_t *group,u_int id); |
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/* Find the highest CPU ID in a CPU group */ |
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int cpu_group_find_highest_id(cpu_group_t *group,u_int *highest_id); |
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/* Add a CPU in a CPU group */ |
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int cpu_group_add(cpu_group_t *group,cpu_gen_t *cpu); |
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/* Create a new CPU group */ |
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cpu_group_t *cpu_group_create(char *name); |
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/* Delete a CPU group */ |
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void cpu_group_delete(cpu_group_t *group); |
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/* Rebuild the MTS subsystem for a CPU group */ |
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int cpu_group_rebuild_mts(cpu_group_t *group); |
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/* Log a message for a CPU */ |
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void cpu_log(cpu_gen_t *cpu,char *module,char *format,...); |
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/* Create a new CPU */ |
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cpu_gen_t *cpu_create(vm_instance_t *vm,u_int type,u_int id); |
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/* Delete a CPU */ |
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void cpu_delete(cpu_gen_t *cpu); |
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/* Start a CPU */ |
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void cpu_start(cpu_gen_t *cpu); |
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/* Stop a CPU */ |
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void cpu_stop(cpu_gen_t *cpu); |
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/* Start all CPUs of a CPU group */ |
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void cpu_group_start_all_cpu(cpu_group_t *group); |
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/* Stop all CPUs of a CPU group */ |
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void cpu_group_stop_all_cpu(cpu_group_t *group); |
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/* Set a state of all CPUs of a CPU group */ |
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void cpu_group_set_state(cpu_group_t *group,u_int state); |
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/* Synchronize on CPUs (all CPUs must be inactive) */ |
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int cpu_group_sync_state(cpu_group_t *group); |
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/* Save state of all CPUs */ |
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int cpu_group_save_state(cpu_group_t *group); |
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/* Restore state of all CPUs */ |
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int cpu_group_restore_state(cpu_group_t *group); |
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/* Virtual idle loop */ |
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void cpu_idle_loop(cpu_gen_t *cpu); |
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/* Break idle wait state */ |
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void cpu_idle_break_wait(cpu_gen_t *cpu); |
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/* Returns to the CPU exec loop */ |
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static inline void cpu_exec_loop_enter(cpu_gen_t *cpu) |
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{ |
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longjmp(cpu->exec_loop_env,1); |
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} |
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/* Set the exec loop entry point */ |
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#define cpu_exec_loop_set(cpu) setjmp((cpu)->exec_loop_env) |
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#endif |