io/macio/macio.cc

/*
 *      PearPC
 *      pci.cc
 *
 *      Copyright (C) 2003 Sebastian Biallas (sb@biallas.net)
 *
 *      This program is free software; you can redistribute it and/or modify
 *      it under the terms of the GNU General Public License version 2 as
 *      published by the Free Software Foundation.
 *
 *      This program is distributed in the hope that it will be useful,
 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *      GNU General Public License for more details.
 *
 *      You should have received a copy of the GNU General Public License
 *      along with this program; if not, write to the Free Software
 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include "debug/tracers.h"
#include "macio.h"

#define MACIO_DBDMA_ADDRESS_CONTROL     0x00
#define MACIO_DBDMA_ADDRESS_STATUS      0x04
#define MACIO_DBDMA_ADDRESS_CMD_PTR_HI  0x08
#define MACIO_DBDMA_ADDRESS_CMD_PTR_LO  0x0c
#define MACIO_DBDMA_ADDRESS_INTR_SEL    0x10
#define MACIO_DBDMA_ADDRESS_BRANCH_SEL  0x14
#define MACIO_DBDMA_ADDRESS_WAIT_SEL    0x18
#define MACIO_DBDMA_ADDRESS_MODES       0x1c
#define MACIO_DBDMA_ADDRESS_DATA_PTR_HI 0x20
#define MACIO_DBDMA_ADDRESS_DATA_PTR_LO 0x24
#define MACIO_DBDMA_ADDRESS_ADDRESS_HI  0x2c
        
/*
 *      Channel control and status flags
 */
#define MACIO_DBDMA_RUN         0x8000
#define MACIO_DBDMA_PAUSE       0x4000
#define MACIO_DBDMA_FLUSH       0x2000
#define MACIO_DBDMA_WAKE        0x1000
#define MACIO_DBDMA_DEAD        0x800
#define MACIO_DBDMA_ACTIVE      0x400
#define MACIO_DBDMA_BT          0x100
#define MACIO_DBDMA_S7          0x80
#define MACIO_DBDMA_S6          0x40
#define MACIO_DBDMA_S5          0x20
#define MACIO_DBDMA_S4          0x10
#define MACIO_DBDMA_S3          0x8
#define MACIO_DBDMA_S2          0x4
#define MACIO_DBDMA_S1          0x2
#define MACIO_DBDMA_S0          0x1

/*
 *      commands
 */

#define MACIO_DBDMA_CMD_OUTPUT_MORE     0
#define MACIO_DBDMA_CMD_OUTPUT_LAST     1
#define MACIO_DBDMA_CMD_INPUT_MORE      2
#define MACIO_DBDMA_CMD_INPUT_LAST      3
#define MACIO_DBDMA_CMD_STORE_QUAD      4
#define MACIO_DBDMA_CMD_LOAD_QUAD       5
#define MACIO_DBDMA_CMD_NOP             6
#define MACIO_DBDMA_CMD_STOP            7

/*
 *      keys
 */

#define  MACIO_DBDMA_KEY_STREAM0        0
#define  MACIO_DBDMA_KEY_STREAM1        1
#define  MACIO_DBDMA_KEY_STREAM2        2
#define  MACIO_DBDMA_KEY_STREAM3        3
#define  MACIO_DBDMA_KEY_REGS           5
#define  MACIO_DBDMA_KEY_SYSTEM         6
#define  MACIO_DBDMA_KEY_DEVICE         7

#define  MACIO_DBDMA_INT_NEVER          0
#define  MACIO_DBDMA_INT_IF_TRUE        1
#define  MACIO_DBDMA_INT_IF_FALSE       2
#define  MACIO_DBDMA_INT_ALWAYS         3

#define  MACIO_DBDMA_BRANCH_NEVER       0
#define  MACIO_DBDMA_BRANCH_IF_TRUE     1
#define  MACIO_DBDMA_BRANCH_IF_FALSE    2
#define  MACIO_DBDMA_BRANCH_ALWAYS      3

#define  MACIO_DBDMA_WAIT_NEVER         0
#define  MACIO_DBDMA_WAIT_IF_TRUE       1
#define  MACIO_DBDMA_WAIT_IF_FALSE      2
#define  MACIO_DBDMA_WAIT_ALWAYS        3

struct MacIO_DBDMA_ChannelRegs {
        uint32 control;
        uint32 status;
        uint32 commandPtrHi;
        uint32 commandPtrLo;
        uint32 interruptSelect;
        uint32 branchSelect;
        uint32 waitSelect;
        uint32 transferModes;
        uint32 data2PtrHi;
        uint32 data2PtrLo;
        uint32 addressHi;
};
 
PCI_MacIO::PCI_MacIO()
        :PCI_Device("pci-macio", 0x01, 0x05)
{
        mIORegSize[0] = 0x80000;
        mIORegType[0] = PCI_ADDRESS_SPACE_MEM;

        mConfig[0x00] = 0x6b;   // vendor ID
        mConfig[0x01] = 0x10;
        mConfig[0x02] = 0x17;   // unit ID
        mConfig[0x03] = 0x00;

        mConfig[0x08] = 0x00;   // revision
        mConfig[0x09] = 0x00;   // programming interface code
        mConfig[0x0a] = 0x00;   // pci2pci
        mConfig[0x0b] = 0xff;   // bridge

        mConfig[0x0e] = 0x00;   // header-type

        assignMemAddress(0, 0x80800000);

        mConfig[0x3c] = 0x18;
        mConfig[0x3d] = 1;
        mConfig[0x3e] = 0;
        mConfig[0x3f] = 0;      
}

bool PCI_MacIO::readDeviceMem(uint r, uint32 address, uint32 &data, uint size)
{
        if (r==0 && address >= 0x8000 && address < 0x8100) {
                address -= 0x8000;
                IO_MACIO_TRACE("dbdma: read(%d) @%08x\n", size, address);
                if (size != 4) IO_MACIO_ERR("read with size != 4\n");
                data = 0;
                switch (address) {
                case MACIO_DBDMA_ADDRESS_CONTROL:
                        return true;
                case MACIO_DBDMA_ADDRESS_STATUS:
                        return true;
                case MACIO_DBDMA_ADDRESS_CMD_PTR_HI:
                        return true;
                case MACIO_DBDMA_ADDRESS_CMD_PTR_LO:
                        return true;
                case MACIO_DBDMA_ADDRESS_INTR_SEL:
                        return true;
                case MACIO_DBDMA_ADDRESS_BRANCH_SEL:
                        return true;
                case MACIO_DBDMA_ADDRESS_WAIT_SEL:
                        return true;
                case MACIO_DBDMA_ADDRESS_MODES:
                        return true;
                case MACIO_DBDMA_ADDRESS_DATA_PTR_HI:
                        return true;
                case MACIO_DBDMA_ADDRESS_DATA_PTR_LO:
                        return true;
                case MACIO_DBDMA_ADDRESS_ADDRESS_HI:
                        return true;
                }
        }
        return false;
}

bool PCI_MacIO::writeDeviceMem(uint r, uint32 address, uint32 data, uint size)
{
        if (r==0 && address >= 0x8000 && address < 0x8100) {
                address -= 0x8000;
                IO_MACIO_TRACE("dbdma: write(%d) @%08x: %08x\n", size, address, data);
                if (size != 4) IO_MACIO_ERR("read with size != 4\n");
                switch (address) {
                case MACIO_DBDMA_ADDRESS_CONTROL:
                        return true;
                case MACIO_DBDMA_ADDRESS_STATUS:
                        return true;
                case MACIO_DBDMA_ADDRESS_CMD_PTR_HI:
                        return true;
                case MACIO_DBDMA_ADDRESS_CMD_PTR_LO:
                        return true;
                case MACIO_DBDMA_ADDRESS_INTR_SEL:
                        return true;
                case MACIO_DBDMA_ADDRESS_BRANCH_SEL:
                        return true;
                case MACIO_DBDMA_ADDRESS_WAIT_SEL:
                        return true;
                case MACIO_DBDMA_ADDRESS_MODES:
                        return true;
                case MACIO_DBDMA_ADDRESS_DATA_PTR_HI:
                        return true;
                case MACIO_DBDMA_ADDRESS_DATA_PTR_LO:
                        return true;
                case MACIO_DBDMA_ADDRESS_ADDRESS_HI:
                        return true;
                }
        }
        return false;
}

void macio_init()
{
        gPCI_Devices->insert(new PCI_MacIO());
}

void macio_done()
{
}

void macio_init_config()
{
}
1	/*
2	* PearPC
3	* pci.cc
4	*
5	* Copyright (C) 2003 Sebastian Biallas (sb@biallas.net)
6	*
7	* This program is free software; you can redistribute it and/or modify
8	* it under the terms of the GNU General Public License version 2 as
9	* published by the Free Software Foundation.
10	*
11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.
15	*
16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19	*/
20
21	#include "debug/tracers.h"
22	#include "macio.h"
23
24	#define MACIO_DBDMA_ADDRESS_CONTROL 0x00
25	#define MACIO_DBDMA_ADDRESS_STATUS 0x04
26	#define MACIO_DBDMA_ADDRESS_CMD_PTR_HI 0x08
27	#define MACIO_DBDMA_ADDRESS_CMD_PTR_LO 0x0c
28	#define MACIO_DBDMA_ADDRESS_INTR_SEL 0x10
29	#define MACIO_DBDMA_ADDRESS_BRANCH_SEL 0x14
30	#define MACIO_DBDMA_ADDRESS_WAIT_SEL 0x18
31	#define MACIO_DBDMA_ADDRESS_MODES 0x1c
32	#define MACIO_DBDMA_ADDRESS_DATA_PTR_HI 0x20
33	#define MACIO_DBDMA_ADDRESS_DATA_PTR_LO 0x24
34	#define MACIO_DBDMA_ADDRESS_ADDRESS_HI 0x2c
35
36	/*
37	* Channel control and status flags
38	*/
39	#define MACIO_DBDMA_RUN 0x8000
40	#define MACIO_DBDMA_PAUSE 0x4000
41	#define MACIO_DBDMA_FLUSH 0x2000
42	#define MACIO_DBDMA_WAKE 0x1000
43	#define MACIO_DBDMA_DEAD 0x800
44	#define MACIO_DBDMA_ACTIVE 0x400
45	#define MACIO_DBDMA_BT 0x100
46	#define MACIO_DBDMA_S7 0x80
47	#define MACIO_DBDMA_S6 0x40
48	#define MACIO_DBDMA_S5 0x20
49	#define MACIO_DBDMA_S4 0x10
50	#define MACIO_DBDMA_S3 0x8
51	#define MACIO_DBDMA_S2 0x4
52	#define MACIO_DBDMA_S1 0x2
53	#define MACIO_DBDMA_S0 0x1
54
55	/*
56	* commands
57	*/
58
59	#define MACIO_DBDMA_CMD_OUTPUT_MORE 0
60	#define MACIO_DBDMA_CMD_OUTPUT_LAST 1
61	#define MACIO_DBDMA_CMD_INPUT_MORE 2
62	#define MACIO_DBDMA_CMD_INPUT_LAST 3
63	#define MACIO_DBDMA_CMD_STORE_QUAD 4
64	#define MACIO_DBDMA_CMD_LOAD_QUAD 5
65	#define MACIO_DBDMA_CMD_NOP 6
66	#define MACIO_DBDMA_CMD_STOP 7
67
68	/*
69	* keys
70	*/
71
72	#define MACIO_DBDMA_KEY_STREAM0 0
73	#define MACIO_DBDMA_KEY_STREAM1 1
74	#define MACIO_DBDMA_KEY_STREAM2 2
75	#define MACIO_DBDMA_KEY_STREAM3 3
76	#define MACIO_DBDMA_KEY_REGS 5
77	#define MACIO_DBDMA_KEY_SYSTEM 6
78	#define MACIO_DBDMA_KEY_DEVICE 7
79
80	#define MACIO_DBDMA_INT_NEVER 0
81	#define MACIO_DBDMA_INT_IF_TRUE 1
82	#define MACIO_DBDMA_INT_IF_FALSE 2
83	#define MACIO_DBDMA_INT_ALWAYS 3
84
85	#define MACIO_DBDMA_BRANCH_NEVER 0
86	#define MACIO_DBDMA_BRANCH_IF_TRUE 1
87	#define MACIO_DBDMA_BRANCH_IF_FALSE 2
88	#define MACIO_DBDMA_BRANCH_ALWAYS 3
89
90	#define MACIO_DBDMA_WAIT_NEVER 0
91	#define MACIO_DBDMA_WAIT_IF_TRUE 1
92	#define MACIO_DBDMA_WAIT_IF_FALSE 2
93	#define MACIO_DBDMA_WAIT_ALWAYS 3
94
95	struct MacIO_DBDMA_ChannelRegs {
96	uint32 control;
97	uint32 status;
98	uint32 commandPtrHi;
99	uint32 commandPtrLo;
100	uint32 interruptSelect;
101	uint32 branchSelect;
102	uint32 waitSelect;
103	uint32 transferModes;
104	uint32 data2PtrHi;
105	uint32 data2PtrLo;
106	uint32 addressHi;
107	};
108
109	PCI_MacIO::PCI_MacIO()
110	:PCI_Device("pci-macio", 0x01, 0x05)
111	{
112	mIORegSize[0] = 0x80000;
113	mIORegType[0] = PCI_ADDRESS_SPACE_MEM;
114
115	mConfig[0x00] = 0x6b; // vendor ID
116	mConfig[0x01] = 0x10;
117	mConfig[0x02] = 0x17; // unit ID
118	mConfig[0x03] = 0x00;
119
120	mConfig[0x08] = 0x00; // revision
121	mConfig[0x09] = 0x00; // programming interface code
122	mConfig[0x0a] = 0x00; // pci2pci
123	mConfig[0x0b] = 0xff; // bridge
124
125	mConfig[0x0e] = 0x00; // header-type
126
127	assignMemAddress(0, 0x80800000);
128
129	mConfig[0x3c] = 0x18;
130	mConfig[0x3d] = 1;
131	mConfig[0x3e] = 0;
132	mConfig[0x3f] = 0;
133	}
134
135	bool PCI_MacIO::readDeviceMem(uint r, uint32 address, uint32 &data, uint size)
136	{
137	if (r==0 && address >= 0x8000 && address < 0x8100) {
138	address -= 0x8000;
139	IO_MACIO_TRACE("dbdma: read(%d) @%08x\n", size, address);
140	if (size != 4) IO_MACIO_ERR("read with size != 4\n");
141	data = 0;
142	switch (address) {
143	case MACIO_DBDMA_ADDRESS_CONTROL:
144	return true;
145	case MACIO_DBDMA_ADDRESS_STATUS:
146	return true;
147	case MACIO_DBDMA_ADDRESS_CMD_PTR_HI:
148	return true;
149	case MACIO_DBDMA_ADDRESS_CMD_PTR_LO:
150	return true;
151	case MACIO_DBDMA_ADDRESS_INTR_SEL:
152	return true;
153	case MACIO_DBDMA_ADDRESS_BRANCH_SEL:
154	return true;
155	case MACIO_DBDMA_ADDRESS_WAIT_SEL:
156	return true;
157	case MACIO_DBDMA_ADDRESS_MODES:
158	return true;
159	case MACIO_DBDMA_ADDRESS_DATA_PTR_HI:
160	return true;
161	case MACIO_DBDMA_ADDRESS_DATA_PTR_LO:
162	return true;
163	case MACIO_DBDMA_ADDRESS_ADDRESS_HI:
164	return true;
165	}
166	}
167	return false;
168	}
169
170	bool PCI_MacIO::writeDeviceMem(uint r, uint32 address, uint32 data, uint size)
171	{
172	if (r==0 && address >= 0x8000 && address < 0x8100) {
173	address -= 0x8000;
174	IO_MACIO_TRACE("dbdma: write(%d) @%08x: %08x\n", size, address, data);
175	if (size != 4) IO_MACIO_ERR("read with size != 4\n");
176	switch (address) {
177	case MACIO_DBDMA_ADDRESS_CONTROL:
178	return true;
179	case MACIO_DBDMA_ADDRESS_STATUS:
180	return true;
181	case MACIO_DBDMA_ADDRESS_CMD_PTR_HI:
182	return true;
183	case MACIO_DBDMA_ADDRESS_CMD_PTR_LO:
184	return true;
185	case MACIO_DBDMA_ADDRESS_INTR_SEL:
186	return true;
187	case MACIO_DBDMA_ADDRESS_BRANCH_SEL:
188	return true;
189	case MACIO_DBDMA_ADDRESS_WAIT_SEL:
190	return true;
191	case MACIO_DBDMA_ADDRESS_MODES:
192	return true;
193	case MACIO_DBDMA_ADDRESS_DATA_PTR_HI:
194	return true;
195	case MACIO_DBDMA_ADDRESS_DATA_PTR_LO:
196	return true;
197	case MACIO_DBDMA_ADDRESS_ADDRESS_HI:
198	return true;
199	}
200	}
201	return false;
202	}
203
204	void macio_init()
205	{
206	gPCI_Devices->insert(new PCI_MacIO());
207	}
208
209	void macio_done()
210	{
211	}
212
213	void macio_init_config()
214	{
215	}