| 1 |
/* |
| 2 |
* HT Editor |
| 3 |
* ppcopc.cc |
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* |
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* Copyright (C) 1999-2003 Sebastian Biallas (sb@biallas.net) |
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* Copyright 1994 Free Software Foundation, Inc. |
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* Written by Ian Lance Taylor, Cygnus Support |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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|
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#include "ppcopc.h" |
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|
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/* The functions used to insert and extract complicated operands. */ |
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|
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/* The BA field in an XL form instruction when it must be the same as |
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the BT field in the same instruction. This operand is marked FAKE. |
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The insertion function just copies the BT field into the BA field, |
| 30 |
and the extraction function just checks that the fields are the |
| 31 |
same. */ |
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|
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static uint32 extract_bat(uint32 insn, bool *invalid) |
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{ |
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if (invalid != NULL && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) *invalid = 1; |
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return 0; |
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} |
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|
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/* The BB field in an XL form instruction when it must be the same as |
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the BA field in the same instruction. This operand is marked FAKE. |
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The insertion function just copies the BA field into the BB field, |
| 42 |
and the extraction function just checks that the fields are the |
| 43 |
same. */ |
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|
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static uint32 extract_bba(uint32 insn, bool *invalid) |
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{ |
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if (invalid != NULL && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) *invalid = 1; |
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return 0; |
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} |
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|
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/* The BD field in a B form instruction. The lower two bits are |
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forced to zero. */ |
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|
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|
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static uint32 extract_bd(uint32 insn, bool *invalid) |
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{ |
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if ((insn & 0x8000) != 0) { |
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return (insn & 0xfffc) - 0x10000; |
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} else { |
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return insn & 0xfffc; |
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} |
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} |
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|
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/* The BD field in a B form instruction when the - modifier is used. |
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This modifier means that the branch is not expected to be taken. |
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For chips built to versions of the architecture prior to version 2 |
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(ie. not Power4 compatible), we set the y bit of the BO field to 1 |
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if the offset is negative. When extracting, we require that the y |
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bit be 1 and that the offset be positive, since if the y bit is 0 |
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we just want to print the normal form of the instruction. |
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Power4 compatible targets use two bits, "a", and "t", instead of |
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the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, |
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"at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 |
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in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 |
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for branch on CTR. We only handle the taken/not-taken hint here. */ |
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|
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static uint32 extract_bdm(uint32 insn, bool *invalid) |
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{ |
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if (invalid) { |
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if ((insn & (0x17 << 21)) != (0x06 << 21) |
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&& (insn & (0x1d << 21)) != (0x18 << 21)) |
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*invalid = true; |
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} |
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return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
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} |
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|
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/* The BD field in a B form instruction when the + modifier is used. |
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This is like BDM, above, except that the branch is expected to be |
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taken. */ |
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|
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static uint32 extract_bdp(uint32 insn, bool *invalid) |
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{ |
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if (invalid) { |
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if ((insn & (0x17 << 21)) != (0x07 << 21) |
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&& (insn & (0x1d << 21)) != (0x19 << 21)) |
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*invalid = true; |
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} |
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return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
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} |
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|
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/* Check for legal values of a BO field. */ |
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|
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static bool valid_bo(uint32 value) |
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{ |
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/* Certain encodings have bits that are required to be zero. |
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These are (z must be zero, a & t may be anything): |
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0000z |
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0001z |
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0100z |
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0101z |
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001at |
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011at |
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1a00t |
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1a01t |
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1z1zz |
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*/ |
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switch (value & 0x14) { |
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case 0: |
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return (value & 1) == 0; |
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case 0x4: |
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case 0x10: |
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return true; |
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case 0x14: |
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return value == 0x14; |
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} |
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return false; |
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} |
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|
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/* The BO field in a B form instruction. Warn about attempts to set |
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the field to an illegal value. */ |
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|
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static uint32 extract_bo(uint32 insn, bool *invalid) |
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{ |
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uint32 value; |
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|
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value = (insn >> 21) & 0x1f; |
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if (invalid != NULL && !valid_bo(value)) |
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*invalid = true; |
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return value; |
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} |
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|
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/* The BO field in a B form instruction when the + or - modifier is |
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used. This is like the BO field, but it must be even. When |
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extracting it, we force it to be even. */ |
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|
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static uint32 extract_boe(uint32 insn, bool *invalid) |
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{ |
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uint32 value; |
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|
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value = (insn >> 21) & 0x1f; |
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if (invalid != NULL && !valid_bo(value)) *invalid = true; |
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return value & 0x1e; |
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} |
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|
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/* The DS field in a DS form instruction. This is like D, but the |
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lower two bits are forced to zero. */ |
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|
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|
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static uint32 extract_ds(uint32 insn, bool *invalid) |
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{ |
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if ((insn & 0x8000) != 0) { |
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return (insn & 0xfffc) - 0x10000; |
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} else { |
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return insn & 0xfffc; |
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} |
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} |
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|
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/* The LI field in an I form instruction. The lower two bits are |
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forced to zero. */ |
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|
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|
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static uint32 extract_li(uint32 insn, bool *invalid) |
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{ |
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if ((insn & 0x2000000) != 0) { |
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return (insn & 0x3fffffc) - 0x4000000; |
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} else { |
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return insn & 0x3fffffc; |
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} |
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} |
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|
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/* The MB and ME fields in an M form instruction expressed as a single |
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operand which is itself a bitmask. The extraction function always |
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marks it as invalid, since we never want to recognize an |
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instruction which uses a field of this type. */ |
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|
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static uint32 extract_mbe(uint32 insn, bool *invalid) |
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{ |
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uint32 ret; |
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int mb, me; |
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int i; |
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|
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if (invalid != NULL) *invalid = 1; |
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|
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ret = 0; |
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mb = (insn >> 6) & 0x1f; |
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me = (insn >> 1) & 0x1f; |
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for (i = mb; i < me; i++) ret |= 1 << (31 - i); |
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return ret; |
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} |
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|
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/* The MB or ME field in an MD or MDS form instruction. The high bit |
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is wrapped to the low end. */ |
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|
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|
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static uint32 extract_mb6(uint32 insn, bool *invalid) |
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{ |
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return ((insn >> 6) & 0x1f) | (insn & 0x20); |
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} |
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|
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/* The NB field in an X form instruction. The value 32 is stored as |
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0. */ |
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|
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|
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static uint32 extract_nb(uint32 insn, bool *invalid) |
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{ |
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uint32 ret; |
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|
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ret = (insn >> 11) & 0x1f; |
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if (ret == 0) ret = 32; |
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return ret; |
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} |
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|
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/* The NSI field in a D form instruction. This is the same as the SI |
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field, only negated. The extraction function always marks it as |
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invalid, since we never want to recognize an instruction which uses |
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a field of this type. */ |
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|
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static uint32 extract_nsi(uint32 insn, bool *invalid) |
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{ |
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if (invalid != NULL) *invalid = 1; |
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if ((insn & 0x8000) != 0) { |
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return - ((insn & 0xffff) - 0x10000); |
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} else { |
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return - (insn & 0xffff); |
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} |
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} |
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|
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/* The RA field in a D or X form instruction which is an updating |
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load, which means that the RA field may not be zero and may not |
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equal the RT field. */ |
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|
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/* The RB field in an X form instruction when it must be the same as |
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the RS field in the instruction. This is used for extended |
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mnemonics like mr. This operand is marked FAKE. The insertion |
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function just copies the BT field into the BA field, and the |
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extraction function just checks that the fields are the same. */ |
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|
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static uint32 extract_rbs(uint32 insn, bool *invalid) |
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{ |
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if (invalid != NULL |
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&& ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) |
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*invalid = 1; |
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return 0; |
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} |
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|
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/* The SH field in an MD form instruction. This is split. */ |
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|
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static uint32 extract_sh6(uint32 insn, bool *invalid) |
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{ |
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return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
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} |
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|
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/* The SPR field in an XFX form instruction. This is flipped--the |
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lower 5 bits are stored in the upper 5 and vice- versa. */ |
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|
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static uint32 extract_spr(uint32 insn, bool *invalid) |
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{ |
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return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
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} |
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|
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/* The TBR field in an XFX instruction. This is just like SPR, but it |
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is optional. When TBR is omitted, it must be inserted as 268 (the |
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magic number of the TB register). These functions treat 0 |
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(indicating an omitted optional operand) as 268. This means that |
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``mftb 4,0'' is not handled correctly. This does not matter very |
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much, since the architecture manual does not define mftb as |
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accepting any values other than 268 or 269. */ |
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|
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#define TB (268) |
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|
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static uint32 extract_tbr(uint32 insn, bool *invalid) |
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{ |
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uint32 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
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if (ret == TB) ret = 0; |
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return ret; |
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} |
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|
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/* The operands table. |
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|
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The fields are bits, shift, signed, extract, flags. */ |
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|
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#undef UNUSED |
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|
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const struct powerpc_operand powerpc_operands[] = |
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{ |
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/* The zero index is used to indicate the end of the list of |
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operands. */ |
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#define UNUSED 0 |
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{ 0, 0, 0, 0 }, |
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|
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/* The BA field in an XL form instruction. */ |
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#define BA UNUSED + 1 |
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#define BA_MASK (0x1f << 16) |
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{ 5, 16, 0, PPC_OPERAND_CR }, |
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|
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/* The BA field in an XL form instruction when it must be the same |
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as the BT field in the same instruction. */ |
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#define BAT BA + 1 |
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{ 5, 16, extract_bat, PPC_OPERAND_FAKE }, |
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|
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/* The BB field in an XL form instruction. */ |
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#define BB BAT + 1 |
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#define BB_MASK (0x1f << 11) |
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{ 5, 11, 0, PPC_OPERAND_CR }, |
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|
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/* The BB field in an XL form instruction when it must be the same |
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as the BA field in the same instruction. */ |
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#define BBA BB + 1 |
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{ 5, 11, extract_bba, PPC_OPERAND_FAKE }, |
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|
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/* The BD field in a B form instruction. The lower two bits are |
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forced to zero. */ |
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#define BD BBA + 1 |
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{ 16, 0, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
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|
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/* The BD field in a B form instruction when absolute addressing is |
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used. */ |
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#define BDA BD + 1 |
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{ 16, 0, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
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|
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/* The BD field in a B form instruction when the - modifier is used. |
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This sets the y bit of the BO field appropriately. */ |
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#define BDM BDA + 1 |
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{ 16, 0, extract_bdm, |
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PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
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|
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/* The BD field in a B form instruction when the - modifier is used |
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and absolute address is used. */ |
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#define BDMA BDM + 1 |
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{ 16, 0, extract_bdm, |
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PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
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|
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/* The BD field in a B form instruction when the + modifier is used. |
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This sets the y bit of the BO field appropriately. */ |
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#define BDP BDMA + 1 |
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{ 16, 0, extract_bdp, |
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PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
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|
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/* The BD field in a B form instruction when the + modifier is used |
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and absolute addressing is used. */ |
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#define BDPA BDP + 1 |
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{ 16, 0, extract_bdp, |
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PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
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|
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/* The BF field in an X or XL form instruction. */ |
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#define BF BDPA + 1 |
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{ 3, 23, 0, PPC_OPERAND_CR }, |
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|
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/* An optional BF field. This is used for comparison instructions, |
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in which an omitted BF field is taken as zero. */ |
| 361 |
#define OBF BF + 1 |
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{ 3, 23, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
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|
| 364 |
/* The BFA field in an X or XL form instruction. */ |
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#define BFA OBF + 1 |
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{ 3, 18, 0, PPC_OPERAND_CR }, |
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|
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/* The BI field in a B form or XL form instruction. */ |
| 369 |
#define BI BFA + 1 |
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#define BI_MASK (0x1f << 16) |
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{ 5, 16, 0, PPC_OPERAND_CR }, |
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|
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/* The BO field in a B form instruction. Certain values are |
| 374 |
illegal. */ |
| 375 |
#define BO BI + 1 |
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#define BO_MASK (0x1f << 21) |
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{ 5, 21, extract_bo, 0 }, |
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|
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/* The BO field in a B form instruction when the + or - modifier is |
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used. This is like the BO field, but it must be even. */ |
| 381 |
#define BOE BO + 1 |
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{ 5, 21, extract_boe, 0 }, |
| 383 |
|
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/* The BT field in an X or XL form instruction. */ |
| 385 |
#define BT BOE + 1 |
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{ 5, 21, 0, PPC_OPERAND_CR }, |
| 387 |
|
| 388 |
/* The condition register number portion of the BI field in a B form |
| 389 |
or XL form instruction. This is used for the extended |
| 390 |
conditional branch mnemonics, which set the lower two bits of the |
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BI field. This field is optional. */ |
| 392 |
#define CR BT + 1 |
| 393 |
{ 3, 18, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
| 394 |
|
| 395 |
/* The CRB field in an X form instruction. */ |
| 396 |
#define CRB CR + 1 |
| 397 |
{ 5, 6, 0, 0 }, |
| 398 |
|
| 399 |
/* The CRFD field in an X form instruction. */ |
| 400 |
#define CRFD CRB + 1 |
| 401 |
{ 3, 23, 0, PPC_OPERAND_CR }, |
| 402 |
|
| 403 |
/* The CRFS field in an X form instruction. */ |
| 404 |
#define CRFS CRFD + 1 |
| 405 |
{ 3, 0, 0, PPC_OPERAND_CR }, |
| 406 |
|
| 407 |
/* The CT field in an X form instruction. */ |
| 408 |
#define CT CRFS + 1 |
| 409 |
{ 5, 21, 0, PPC_OPERAND_OPTIONAL }, |
| 410 |
|
| 411 |
/* The D field in a D form instruction. This is a displacement off |
| 412 |
a register, and implies that the next operand is a register in |
| 413 |
parentheses. */ |
| 414 |
#define D CT + 1 |
| 415 |
{ 16, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
| 416 |
|
| 417 |
/* The DS field in a DS form instruction. This is like D, but the |
| 418 |
lower two bits are forced to zero. */ |
| 419 |
#define DS D + 1 |
| 420 |
{ 16, 0, extract_ds, |
| 421 |
PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, |
| 422 |
|
| 423 |
/* The FLM field in an XFL form instruction. */ |
| 424 |
#define FLM DS + 1 |
| 425 |
{ 8, 17, 0, 0 }, |
| 426 |
|
| 427 |
/* The FRA field in an X or A form instruction. */ |
| 428 |
#define FRA FLM + 1 |
| 429 |
#define FRA_MASK (0x1f << 16) |
| 430 |
{ 5, 16, 0, PPC_OPERAND_FPR }, |
| 431 |
|
| 432 |
/* The FRB field in an X or A form instruction. */ |
| 433 |
#define FRB FRA + 1 |
| 434 |
#define FRB_MASK (0x1f << 11) |
| 435 |
{ 5, 11, 0, PPC_OPERAND_FPR }, |
| 436 |
|
| 437 |
/* The FRC field in an A form instruction. */ |
| 438 |
#define FRC FRB + 1 |
| 439 |
#define FRC_MASK (0x1f << 6) |
| 440 |
{ 5, 6, 0, PPC_OPERAND_FPR }, |
| 441 |
|
| 442 |
/* The FRS field in an X form instruction or the FRT field in a D, X |
| 443 |
or A form instruction. */ |
| 444 |
#define FRS FRC + 1 |
| 445 |
#define FRT FRS |
| 446 |
{ 5, 21, 0, PPC_OPERAND_FPR }, |
| 447 |
|
| 448 |
/* The FXM field in an XFX instruction. */ |
| 449 |
#define FXM FRS + 1 |
| 450 |
#define FXM_MASK (0xff << 12) |
| 451 |
{ 8, 12, 0, 0 }, |
| 452 |
|
| 453 |
/* The L field in a D or X form instruction. */ |
| 454 |
#define L FXM + 1 |
| 455 |
{ 1, 21, 0, PPC_OPERAND_OPTIONAL }, |
| 456 |
|
| 457 |
/* The LI field in an I form instruction. The lower two bits are |
| 458 |
forced to zero. */ |
| 459 |
#define LI L + 1 |
| 460 |
{ 26, 0, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| 461 |
|
| 462 |
/* The LI field in an I form instruction when used as an absolute |
| 463 |
address. */ |
| 464 |
#define LIA LI + 1 |
| 465 |
{ 26, 0, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
| 466 |
|
| 467 |
/* The LS field in an X (sync) form instruction. */ |
| 468 |
#define LS LIA + 1 |
| 469 |
{ 2, 21, 0, PPC_OPERAND_OPTIONAL }, |
| 470 |
|
| 471 |
/* The MB field in an M form instruction. */ |
| 472 |
#define MB LS + 1 |
| 473 |
#define MB_MASK (0x1f << 6) |
| 474 |
{ 5, 6, 0, 0 }, |
| 475 |
|
| 476 |
/* The ME field in an M form instruction. */ |
| 477 |
#define ME MB + 1 |
| 478 |
#define ME_MASK (0x1f << 1) |
| 479 |
{ 5, 1, 0, 0 }, |
| 480 |
|
| 481 |
/* The MB and ME fields in an M form instruction expressed a single |
| 482 |
operand which is a bitmask indicating which bits to select. This |
| 483 |
is a two operand form using PPC_OPERAND_NEXT. See the |
| 484 |
description in opcode/ppc.h for what this means. */ |
| 485 |
#define MBE ME + 1 |
| 486 |
{ 5, 6, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, |
| 487 |
{ 32, 0, extract_mbe, 0 }, |
| 488 |
|
| 489 |
/* The MB or ME field in an MD or MDS form instruction. The high |
| 490 |
bit is wrapped to the low end. */ |
| 491 |
#define MB6 MBE + 2 |
| 492 |
#define ME6 MB6 |
| 493 |
#define MB6_MASK (0x3f << 5) |
| 494 |
{ 6, 5, extract_mb6, 0 }, |
| 495 |
|
| 496 |
/* The MO field in an mbar instruction. */ |
| 497 |
#define MO MB6 + 1 |
| 498 |
{ 5, 21, 0, 0 }, |
| 499 |
|
| 500 |
/* The NB field in an X form instruction. The value 32 is stored as |
| 501 |
0. */ |
| 502 |
#define NB MO + 1 |
| 503 |
{ 6, 11, extract_nb, 0 }, |
| 504 |
|
| 505 |
/* The NSI field in a D form instruction. This is the same as the |
| 506 |
SI field, only negated. */ |
| 507 |
#define NSI NB + 1 |
| 508 |
{ 16, 0, extract_nsi, |
| 509 |
PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
| 510 |
|
| 511 |
/* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ |
| 512 |
#define RA NSI + 1 |
| 513 |
#define RA_MASK (0x1f << 16) |
| 514 |
{ 5, 16, 0, PPC_OPERAND_GPR }, |
| 515 |
|
| 516 |
/* The RA field in a D or X form instruction which is an updating |
| 517 |
load, which means that the RA field may not be zero and may not |
| 518 |
equal the RT field. */ |
| 519 |
#define RAL RA + 1 |
| 520 |
{ 5, 16, 0, PPC_OPERAND_GPR }, |
| 521 |
|
| 522 |
/* The RA field in an lmw instruction, which has special value |
| 523 |
restrictions. */ |
| 524 |
#define RAM RAL + 1 |
| 525 |
{ 5, 16, 0, PPC_OPERAND_GPR }, |
| 526 |
|
| 527 |
/* The RA field in a D or X form instruction which is an updating |
| 528 |
store or an updating floating point load, which means that the RA |
| 529 |
field may not be zero. */ |
| 530 |
#define RAS RAM + 1 |
| 531 |
{ 5, 16, 0, PPC_OPERAND_GPR }, |
| 532 |
|
| 533 |
/* The RB field in an X, XO, M, or MDS form instruction. */ |
| 534 |
#define RB RAS + 1 |
| 535 |
#define RB_MASK (0x1f << 11) |
| 536 |
{ 5, 11, 0, PPC_OPERAND_GPR }, |
| 537 |
|
| 538 |
/* The RB field in an X form instruction when it must be the same as |
| 539 |
the RS field in the instruction. This is used for extended |
| 540 |
mnemonics like mr. */ |
| 541 |
#define RBS RB + 1 |
| 542 |
{ 5, 1, extract_rbs, PPC_OPERAND_FAKE }, |
| 543 |
|
| 544 |
/* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form |
| 545 |
instruction or the RT field in a D, DS, X, XFX or XO form |
| 546 |
instruction. */ |
| 547 |
#define RS RBS + 1 |
| 548 |
#define RT RS |
| 549 |
#define RT_MASK (0x1f << 21) |
| 550 |
{ 5, 21, 0, PPC_OPERAND_GPR }, |
| 551 |
|
| 552 |
/* The SH field in an X or M form instruction. */ |
| 553 |
#define SH RS + 1 |
| 554 |
#define SH_MASK (0x1f << 11) |
| 555 |
{ 5, 11, 0, 0 }, |
| 556 |
|
| 557 |
/* The SH field in an MD form instruction. This is split. */ |
| 558 |
#define SH6 SH + 1 |
| 559 |
#define SH6_MASK ((0x1f << 11) | (1 << 1)) |
| 560 |
{ 6, 1, extract_sh6, 0 }, |
| 561 |
|
| 562 |
/* The SI field in a D form instruction. */ |
| 563 |
#define SI SH6 + 1 |
| 564 |
{ 16, 0, 0, PPC_OPERAND_SIGNED }, |
| 565 |
|
| 566 |
/* The SI field in a D form instruction when we accept a wide range |
| 567 |
of positive values. */ |
| 568 |
#define SISIGNOPT SI + 1 |
| 569 |
{ 16, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
| 570 |
|
| 571 |
/* The SPR field in an XFX form instruction. This is flipped--the |
| 572 |
lower 5 bits are stored in the upper 5 and vice- versa. */ |
| 573 |
#define SPR SISIGNOPT + 1 |
| 574 |
#define PMR SPR |
| 575 |
#define SPR_MASK (0x3ff << 11) |
| 576 |
{ 10, 11, extract_spr, 0 }, |
| 577 |
|
| 578 |
/* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ |
| 579 |
#define SPRBAT SPR + 1 |
| 580 |
#define SPRBAT_MASK (0x3 << 17) |
| 581 |
{ 2, 17, 0, 0 }, |
| 582 |
|
| 583 |
/* The SPRG register number in an XFX form m[ft]sprg instruction. */ |
| 584 |
#define SPRG SPRBAT + 1 |
| 585 |
#define SPRG_MASK (0x3 << 16) |
| 586 |
{ 2, 16, 0, 0 }, |
| 587 |
|
| 588 |
/* The SR field in an X form instruction. */ |
| 589 |
#define SR SPRG + 1 |
| 590 |
{ 4, 16, 0, 0 }, |
| 591 |
|
| 592 |
/* The STRM field in an X AltiVec form instruction. */ |
| 593 |
#define STRM SR + 1 |
| 594 |
#define STRM_MASK (0x3 << 21) |
| 595 |
{ 2, 21, 0, 0 }, |
| 596 |
|
| 597 |
/* The SV field in a POWER SC form instruction. */ |
| 598 |
#define SV STRM + 1 |
| 599 |
{ 14, 2, 0, 0 }, |
| 600 |
|
| 601 |
/* The TBR field in an XFX form instruction. This is like the SPR |
| 602 |
field, but it is optional. */ |
| 603 |
#define TBR SV + 1 |
| 604 |
{ 10, 11, extract_tbr, PPC_OPERAND_OPTIONAL }, |
| 605 |
|
| 606 |
/* The TO field in a D or X form instruction. */ |
| 607 |
#define TO TBR + 1 |
| 608 |
#define TO_MASK (0x1f << 21) |
| 609 |
{ 5, 21, 0, 0 }, |
| 610 |
|
| 611 |
/* The U field in an X form instruction. */ |
| 612 |
#define U TO + 1 |
| 613 |
{ 4, 12, 0, 0 }, |
| 614 |
|
| 615 |
/* The UI field in a D form instruction. */ |
| 616 |
#define UI U + 1 |
| 617 |
{ 16, 0, 0, 0 }, |
| 618 |
|
| 619 |
/* The VA field in a VA, VX or VXR form instruction. */ |
| 620 |
#define VA UI + 1 |
| 621 |
#define VA_MASK (0x1f << 16) |
| 622 |
{ 5, 16, 0, PPC_OPERAND_VR }, |
| 623 |
|
| 624 |
/* The VB field in a VA, VX or VXR form instruction. */ |
| 625 |
#define VB VA + 1 |
| 626 |
#define VB_MASK (0x1f << 11) |
| 627 |
{ 5, 11, 0, PPC_OPERAND_VR }, |
| 628 |
|
| 629 |
/* The VC field in a VA form instruction. */ |
| 630 |
#define VC VB + 1 |
| 631 |
#define VC_MASK (0x1f << 6) |
| 632 |
{ 5, 6, 0, PPC_OPERAND_VR }, |
| 633 |
|
| 634 |
/* The VD or VS field in a VA, VX, VXR or X form instruction. */ |
| 635 |
#define VD VC + 1 |
| 636 |
#define VS VD |
| 637 |
#define VD_MASK (0x1f << 21) |
| 638 |
{ 5, 21, 0, PPC_OPERAND_VR }, |
| 639 |
|
| 640 |
/* The SIMM field in a VX form instruction. */ |
| 641 |
#define SIMM VD + 1 |
| 642 |
{ 5, 16, 0, PPC_OPERAND_SIGNED}, |
| 643 |
|
| 644 |
/* The UIMM field in a VX form instruction. */ |
| 645 |
#define UIMM SIMM + 1 |
| 646 |
{ 5, 16, 0, 0 }, |
| 647 |
|
| 648 |
/* The SHB field in a VA form instruction. */ |
| 649 |
#define SHB UIMM + 1 |
| 650 |
{ 4, 6, 0, 0 }, |
| 651 |
|
| 652 |
/* The WS field. */ |
| 653 |
#define WS SHB + 1 |
| 654 |
#define WS_MASK (0x7 << 11) |
| 655 |
{ 3, 11, 0, 0 }, |
| 656 |
|
| 657 |
/* The L field in an mtmsrd instruction */ |
| 658 |
#define MTMSRD_L WS + 1 |
| 659 |
{ 1, 16, 0, PPC_OPERAND_OPTIONAL }, |
| 660 |
}; |
| 661 |
|
| 662 |
|
| 663 |
/* Macros used to form opcodes. */ |
| 664 |
|
| 665 |
/* The main opcode. */ |
| 666 |
#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) |
| 667 |
#define OP_MASK OP (0x3f) |
| 668 |
|
| 669 |
/* The main opcode combined with a trap code in the TO field of a D |
| 670 |
form instruction. Used for extended mnemonics for the trap |
| 671 |
instructions. */ |
| 672 |
#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) |
| 673 |
#define OPTO_MASK (OP_MASK | TO_MASK) |
| 674 |
|
| 675 |
/* The main opcode combined with a comparison size bit in the L field |
| 676 |
of a D form or X form instruction. Used for extended mnemonics for |
| 677 |
the comparison instructions. */ |
| 678 |
#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) |
| 679 |
#define OPL_MASK OPL (0x3f,1) |
| 680 |
|
| 681 |
/* An A form instruction. */ |
| 682 |
#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) |
| 683 |
#define A_MASK A (0x3f, 0x1f, 1) |
| 684 |
|
| 685 |
/* An A_MASK with the FRB field fixed. */ |
| 686 |
#define AFRB_MASK (A_MASK | FRB_MASK) |
| 687 |
|
| 688 |
/* An A_MASK with the FRC field fixed. */ |
| 689 |
#define AFRC_MASK (A_MASK | FRC_MASK) |
| 690 |
|
| 691 |
/* An A_MASK with the FRA and FRC fields fixed. */ |
| 692 |
#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) |
| 693 |
|
| 694 |
/* A B form instruction. */ |
| 695 |
#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) |
| 696 |
#define B_MASK B (0x3f, 1, 1) |
| 697 |
|
| 698 |
/* A B form instruction setting the BO field. */ |
| 699 |
#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) |
| 700 |
#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) |
| 701 |
|
| 702 |
/* A BBO_MASK with the y bit of the BO field removed. This permits |
| 703 |
matching a conditional branch regardless of the setting of the y |
| 704 |
bit. Similarly for the 'at' bits used for power4 branch hints. */ |
| 705 |
#define Y_MASK (((unsigned long) 1) << 21) |
| 706 |
#define AT1_MASK (((unsigned long) 3) << 21) |
| 707 |
#define AT2_MASK (((unsigned long) 9) << 21) |
| 708 |
#define BBOY_MASK (BBO_MASK &~ Y_MASK) |
| 709 |
#define BBOAT_MASK (BBO_MASK &~ AT1_MASK) |
| 710 |
|
| 711 |
/* A B form instruction setting the BO field and the condition bits of |
| 712 |
the BI field. */ |
| 713 |
#define BBOCB(op, bo, cb, aa, lk) \ |
| 714 |
(BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) |
| 715 |
#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) |
| 716 |
|
| 717 |
/* A BBOCB_MASK with the y bit of the BO field removed. */ |
| 718 |
#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) |
| 719 |
#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) |
| 720 |
#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) |
| 721 |
|
| 722 |
/* A BBOYCB_MASK in which the BI field is fixed. */ |
| 723 |
#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) |
| 724 |
#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) |
| 725 |
|
| 726 |
/* An Context form instruction. */ |
| 727 |
#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) |
| 728 |
#define CTX_MASK CTX(0x3f, 0x7) |
| 729 |
|
| 730 |
/* An User Context form instruction. */ |
| 731 |
#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) |
| 732 |
#define UCTX_MASK UCTX(0x3f, 0x1f) |
| 733 |
|
| 734 |
/* The main opcode mask with the RA field clear. */ |
| 735 |
#define DRA_MASK (OP_MASK | RA_MASK) |
| 736 |
|
| 737 |
/* A DS form instruction. */ |
| 738 |
#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) |
| 739 |
#define DS_MASK DSO (0x3f, 3) |
| 740 |
|
| 741 |
/* A DE form instruction. */ |
| 742 |
#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) |
| 743 |
#define DE_MASK DEO (0x3e, 0xf) |
| 744 |
|
| 745 |
/* An EVSEL form instruction. */ |
| 746 |
#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) |
| 747 |
#define EVSEL_MASK EVSEL(0x3f, 0xff) |
| 748 |
|
| 749 |
/* An M form instruction. */ |
| 750 |
#define M(op, rc) (OP (op) | ((rc) & 1)) |
| 751 |
#define M_MASK M (0x3f, 1) |
| 752 |
|
| 753 |
/* An M form instruction with the ME field specified. */ |
| 754 |
#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) |
| 755 |
|
| 756 |
/* An M_MASK with the MB and ME fields fixed. */ |
| 757 |
#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) |
| 758 |
|
| 759 |
/* An M_MASK with the SH and ME fields fixed. */ |
| 760 |
#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) |
| 761 |
|
| 762 |
/* An MD form instruction. */ |
| 763 |
#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) |
| 764 |
#define MD_MASK MD (0x3f, 0x7, 1) |
| 765 |
|
| 766 |
/* An MD_MASK with the MB field fixed. */ |
| 767 |
#define MDMB_MASK (MD_MASK | MB6_MASK) |
| 768 |
|
| 769 |
/* An MD_MASK with the SH field fixed. */ |
| 770 |
#define MDSH_MASK (MD_MASK | SH6_MASK) |
| 771 |
|
| 772 |
/* An MDS form instruction. */ |
| 773 |
#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) |
| 774 |
#define MDS_MASK MDS (0x3f, 0xf, 1) |
| 775 |
|
| 776 |
/* An MDS_MASK with the MB field fixed. */ |
| 777 |
#define MDSMB_MASK (MDS_MASK | MB6_MASK) |
| 778 |
|
| 779 |
/* An SC form instruction. */ |
| 780 |
#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) |
| 781 |
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) |
| 782 |
|
| 783 |
/* An VX form instruction. */ |
| 784 |
#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) |
| 785 |
|
| 786 |
/* The mask for an VX form instruction. */ |
| 787 |
#define VX_MASK VX(0x3f, 0x7ff) |
| 788 |
|
| 789 |
/* An VA form instruction. */ |
| 790 |
#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) |
| 791 |
|
| 792 |
/* The mask for an VA form instruction. */ |
| 793 |
#define VXA_MASK VXA(0x3f, 0x3f) |
| 794 |
|
| 795 |
/* An VXR form instruction. */ |
| 796 |
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) |
| 797 |
|
| 798 |
/* The mask for a VXR form instruction. */ |
| 799 |
#define VXR_MASK VXR(0x3f, 0x3ff, 1) |
| 800 |
|
| 801 |
/* An X form instruction. */ |
| 802 |
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
| 803 |
|
| 804 |
/* An X form instruction with the RC bit specified. */ |
| 805 |
#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) |
| 806 |
|
| 807 |
/* The mask for an X form instruction. */ |
| 808 |
#define X_MASK XRC (0x3f, 0x3ff, 1) |
| 809 |
|
| 810 |
/* An X_MASK with the RA field fixed. */ |
| 811 |
#define XRA_MASK (X_MASK | RA_MASK) |
| 812 |
|
| 813 |
/* An X_MASK with the RB field fixed. */ |
| 814 |
#define XRB_MASK (X_MASK | RB_MASK) |
| 815 |
|
| 816 |
/* An X_MASK with the RT field fixed. */ |
| 817 |
#define XRT_MASK (X_MASK | RT_MASK) |
| 818 |
|
| 819 |
/* An X_MASK with the RA and RB fields fixed. */ |
| 820 |
#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) |
| 821 |
|
| 822 |
/* An XRARB_MASK, but with the L bit clear. */ |
| 823 |
#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) |
| 824 |
|
| 825 |
/* An X_MASK with the RT and RA fields fixed. */ |
| 826 |
#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) |
| 827 |
|
| 828 |
/* An XRTRA_MASK, but with L bit clear. */ |
| 829 |
#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) |
| 830 |
|
| 831 |
/* An X form comparison instruction. */ |
| 832 |
#define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) |
| 833 |
|
| 834 |
/* The mask for an X form comparison instruction. */ |
| 835 |
#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) |
| 836 |
|
| 837 |
/* The mask for an X form comparison instruction with the L field |
| 838 |
fixed. */ |
| 839 |
#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) |
| 840 |
|
| 841 |
/* An X form trap instruction with the TO field specified. */ |
| 842 |
#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) |
| 843 |
#define XTO_MASK (X_MASK | TO_MASK) |
| 844 |
|
| 845 |
/* An X form tlb instruction with the SH field specified. */ |
| 846 |
#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) |
| 847 |
#define XTLB_MASK (X_MASK | SH_MASK) |
| 848 |
|
| 849 |
/* An X form sync instruction. */ |
| 850 |
#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) |
| 851 |
|
| 852 |
/* An X form sync instruction with everything filled in except the LS field. */ |
| 853 |
#define XSYNC_MASK (0xff9fffff) |
| 854 |
|
| 855 |
/* An X form AltiVec dss instruction. */ |
| 856 |
#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) |
| 857 |
#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) |
| 858 |
|
| 859 |
/* An XFL form instruction. */ |
| 860 |
#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) |
| 861 |
#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) |
| 862 |
|
| 863 |
/* An X form isel instruction. */ |
| 864 |
#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
| 865 |
#define XISEL_MASK XISEL(0x3f, 0x1f) |
| 866 |
|
| 867 |
/* An XL form instruction with the LK field set to 0. */ |
| 868 |
#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
| 869 |
|
| 870 |
/* An XL form instruction which uses the LK field. */ |
| 871 |
#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) |
| 872 |
|
| 873 |
/* The mask for an XL form instruction. */ |
| 874 |
#define XL_MASK XLLK (0x3f, 0x3ff, 1) |
| 875 |
|
| 876 |
/* An XL form instruction which explicitly sets the BO field. */ |
| 877 |
#define XLO(op, bo, xop, lk) \ |
| 878 |
(XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) |
| 879 |
#define XLO_MASK (XL_MASK | BO_MASK) |
| 880 |
|
| 881 |
/* An XL form instruction which explicitly sets the y bit of the BO |
| 882 |
field. */ |
| 883 |
#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) |
| 884 |
#define XLYLK_MASK (XL_MASK | Y_MASK) |
| 885 |
|
| 886 |
/* An XL form instruction which sets the BO field and the condition |
| 887 |
bits of the BI field. */ |
| 888 |
#define XLOCB(op, bo, cb, xop, lk) \ |
| 889 |
(XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) |
| 890 |
#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) |
| 891 |
|
| 892 |
/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ |
| 893 |
#define XLBB_MASK (XL_MASK | BB_MASK) |
| 894 |
#define XLYBB_MASK (XLYLK_MASK | BB_MASK) |
| 895 |
#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) |
| 896 |
|
| 897 |
/* An XL_MASK with the BO and BB fields fixed. */ |
| 898 |
#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) |
| 899 |
|
| 900 |
/* An XL_MASK with the BO, BI and BB fields fixed. */ |
| 901 |
#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) |
| 902 |
|
| 903 |
/* An XO form instruction. */ |
| 904 |
#define XO(op, xop, oe, rc) \ |
| 905 |
(OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) |
| 906 |
#define XO_MASK XO (0x3f, 0x1ff, 1, 1) |
| 907 |
|
| 908 |
/* An XO_MASK with the RB field fixed. */ |
| 909 |
#define XORB_MASK (XO_MASK | RB_MASK) |
| 910 |
|
| 911 |
/* An XS form instruction. */ |
| 912 |
#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) |
| 913 |
#define XS_MASK XS (0x3f, 0x1ff, 1) |
| 914 |
|
| 915 |
/* A mask for the FXM version of an XFX form instruction. */ |
| 916 |
#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11)) |
| 917 |
|
| 918 |
/* An XFX form instruction with the FXM field filled in. */ |
| 919 |
#define XFXM(op, xop, fxm) \ |
| 920 |
(X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12)) |
| 921 |
|
| 922 |
/* An XFX form instruction with the SPR field filled in. */ |
| 923 |
#define XSPR(op, xop, spr) \ |
| 924 |
(X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) |
| 925 |
#define XSPR_MASK (X_MASK | SPR_MASK) |
| 926 |
|
| 927 |
/* An XFX form instruction with the SPR field filled in except for the |
| 928 |
SPRBAT field. */ |
| 929 |
#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) |
| 930 |
|
| 931 |
/* An XFX form instruction with the SPR field filled in except for the |
| 932 |
SPRG field. */ |
| 933 |
#define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK) |
| 934 |
|
| 935 |
/* An X form instruction with everything filled in except the E field. */ |
| 936 |
#define XE_MASK (0xffff7fff) |
| 937 |
|
| 938 |
/* An X form user context instruction. */ |
| 939 |
#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) |
| 940 |
#define XUC_MASK XUC(0x3f, 0x1f) |
| 941 |
|
| 942 |
/* The BO encodings used in extended conditional branch mnemonics. */ |
| 943 |
#define BODNZF (0x0) |
| 944 |
#define BODNZFP (0x1) |
| 945 |
#define BODZF (0x2) |
| 946 |
#define BODZFP (0x3) |
| 947 |
#define BODNZT (0x8) |
| 948 |
#define BODNZTP (0x9) |
| 949 |
#define BODZT (0xa) |
| 950 |
#define BODZTP (0xb) |
| 951 |
|
| 952 |
#define BOF (0x4) |
| 953 |
#define BOFP (0x5) |
| 954 |
#define BOFM4 (0x6) |
| 955 |
#define BOFP4 (0x7) |
| 956 |
#define BOT (0xc) |
| 957 |
#define BOTP (0xd) |
| 958 |
#define BOTM4 (0xe) |
| 959 |
#define BOTP4 (0xf) |
| 960 |
|
| 961 |
#define BODNZ (0x10) |
| 962 |
#define BODNZP (0x11) |
| 963 |
#define BODZ (0x12) |
| 964 |
#define BODZP (0x13) |
| 965 |
#define BODNZM4 (0x18) |
| 966 |
#define BODNZP4 (0x19) |
| 967 |
#define BODZM4 (0x1a) |
| 968 |
#define BODZP4 (0x1b) |
| 969 |
|
| 970 |
#define BOU (0x14) |
| 971 |
|
| 972 |
/* The BI condition bit encodings used in extended conditional branch |
| 973 |
mnemonics. */ |
| 974 |
#define CBLT (0) |
| 975 |
#define CBGT (1) |
| 976 |
#define CBEQ (2) |
| 977 |
#define CBSO (3) |
| 978 |
|
| 979 |
/* The TO encodings used in extended trap mnemonics. */ |
| 980 |
#define TOLGT (0x1) |
| 981 |
#define TOLLT (0x2) |
| 982 |
#define TOEQ (0x4) |
| 983 |
#define TOLGE (0x5) |
| 984 |
#define TOLNL (0x5) |
| 985 |
#define TOLLE (0x6) |
| 986 |
#define TOLNG (0x6) |
| 987 |
#define TOGT (0x8) |
| 988 |
#define TOGE (0xc) |
| 989 |
#define TONL (0xc) |
| 990 |
#define TOLT (0x10) |
| 991 |
#define TOLE (0x14) |
| 992 |
#define TONG (0x14) |
| 993 |
#define TONE (0x18) |
| 994 |
#define TOU (0x1f) |
| 995 |
|
| 996 |
/* Smaller names for the flags so each entry in the opcodes table will |
| 997 |
fit on a single line. */ |
| 998 |
#undef PPC |
| 999 |
#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY |
| 1000 |
#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY |
| 1001 |
#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM |
| 1002 |
#define POWER4 PPC_OPCODE_POWER4 | PPCCOM |
| 1003 |
#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY |
| 1004 |
#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY |
| 1005 |
#define PPCONLY PPC_OPCODE_PPC |
| 1006 |
#define PPC403 PPC_OPCODE_403 |
| 1007 |
#define PPC405 PPC403 |
| 1008 |
#define PPC750 PPC |
| 1009 |
#define PPC860 PPC |
| 1010 |
#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC |
| 1011 |
#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY |
| 1012 |
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY |
| 1013 |
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY |
| 1014 |
#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32 |
| 1015 |
#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY |
| 1016 |
#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32 |
| 1017 |
#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY |
| 1018 |
#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY |
| 1019 |
#define MFDEC1 PPC_OPCODE_POWER |
| 1020 |
#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE |
| 1021 |
#define BOOKE PPC_OPCODE_BOOKE |
| 1022 |
#define BOOKE64 PPC_OPCODE_BOOKE64 |
| 1023 |
#define CLASSIC PPC_OPCODE_CLASSIC |
| 1024 |
#define PPCSPE PPC_OPCODE_SPE |
| 1025 |
#define PPCISEL PPC_OPCODE_ISEL |
| 1026 |
#define PPCEFS PPC_OPCODE_EFS |
| 1027 |
#define PPCBRLK PPC_OPCODE_BRLOCK |
| 1028 |
#define PPCPMR PPC_OPCODE_PMR |
| 1029 |
#define PPCCHLK PPC_OPCODE_CACHELCK |
| 1030 |
#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 |
| 1031 |
#define PPCRFMCI PPC_OPCODE_RFMCI |
| 1032 |
|
| 1033 |
/* The opcode table. |
| 1034 |
|
| 1035 |
The format of the opcode table is: |
| 1036 |
|
| 1037 |
NAME OPCODE MASK FLAGS { OPERANDS } |
| 1038 |
|
| 1039 |
NAME is the name of the instruction. |
| 1040 |
OPCODE is the instruction opcode. |
| 1041 |
MASK is the opcode mask; this is used to tell the disassembler |
| 1042 |
which bits in the actual opcode must match OPCODE. |
| 1043 |
FLAGS are flags indicated what processors support the instruction. |
| 1044 |
OPERANDS is the list of operands. |
| 1045 |
|
| 1046 |
The disassembler reads the table in order and prints the first |
| 1047 |
instruction which matches, so this table is sorted to put more |
| 1048 |
specific instructions before more general instructions. It is also |
| 1049 |
sorted by major opcode. */ |
| 1050 |
|
| 1051 |
const struct powerpc_opcode powerpc_opcodes[] = { |
| 1052 |
|
| 1053 |
{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1054 |
{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1055 |
{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1056 |
{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1057 |
{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1058 |
{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1059 |
{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1060 |
{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1061 |
{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1062 |
{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1063 |
{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1064 |
{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1065 |
{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1066 |
{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1067 |
{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1068 |
{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1069 |
{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1070 |
{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1071 |
{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1072 |
{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1073 |
{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1074 |
{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1075 |
{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1076 |
{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1077 |
{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1078 |
{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1079 |
{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, |
| 1080 |
{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, |
| 1081 |
{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, |
| 1082 |
{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, |
| 1083 |
|
| 1084 |
{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, |
| 1085 |
{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, |
| 1086 |
{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1087 |
{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1088 |
{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1089 |
{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1090 |
{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1091 |
{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1092 |
{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1093 |
{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1094 |
{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1095 |
{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1096 |
{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1097 |
{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1098 |
{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1099 |
{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1100 |
{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1101 |
{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1102 |
{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1103 |
{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1104 |
{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1105 |
{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
| 1106 |
{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
| 1107 |
{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1108 |
{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1109 |
{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1110 |
{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1111 |
{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1112 |
{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1113 |
{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1114 |
{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1115 |
{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1116 |
{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1117 |
{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1118 |
{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1119 |
{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1120 |
{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1121 |
{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1122 |
{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1123 |
{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1124 |
{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1125 |
{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1126 |
{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1127 |
{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1128 |
{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1129 |
{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1130 |
{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1131 |
{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1132 |
{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, |
| 1133 |
{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
| 1134 |
{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
| 1135 |
{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, |
| 1136 |
{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, |
| 1137 |
{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, |
| 1138 |
{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1139 |
{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1140 |
{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1141 |
{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1142 |
{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1143 |
{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1144 |
{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1145 |
{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1146 |
{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1147 |
{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1148 |
{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1149 |
{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1150 |
{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1151 |
{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1152 |
{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1153 |
{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1154 |
{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1155 |
{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1156 |
{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1157 |
{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1158 |
{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1159 |
{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1160 |
{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1161 |
{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1162 |
{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1163 |
{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1164 |
{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1165 |
{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1166 |
{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1167 |
{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1168 |
{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1169 |
{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1170 |
{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1171 |
{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1172 |
{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1173 |
{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1174 |
{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1175 |
{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, |
| 1176 |
{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1177 |
{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1178 |
{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1179 |
{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1180 |
{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1181 |
{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1182 |
{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1183 |
{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1184 |
{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1185 |
{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1186 |
{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1187 |
{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1188 |
{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, |
| 1189 |
{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, |
| 1190 |
{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, |
| 1191 |
{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, |
| 1192 |
{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, |
| 1193 |
{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1194 |
{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1195 |
{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1196 |
{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, |
| 1197 |
{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, |
| 1198 |
{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1199 |
{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1200 |
{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, |
| 1201 |
{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1202 |
{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1203 |
{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1204 |
{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
| 1205 |
{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
| 1206 |
{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, |
| 1207 |
{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, |
| 1208 |
{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, |
| 1209 |
{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, |
| 1210 |
{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1211 |
{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1212 |
{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1213 |
{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1214 |
{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1215 |
{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1216 |
{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1217 |
{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1218 |
{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1219 |
{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1220 |
{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1221 |
{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1222 |
{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1223 |
{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1224 |
{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1225 |
{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1226 |
{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1227 |
{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1228 |
{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1229 |
{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1230 |
{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1231 |
{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1232 |
{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1233 |
{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1234 |
{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, |
| 1235 |
{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, |
| 1236 |
{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, |
| 1237 |
{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, |
| 1238 |
{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, |
| 1239 |
{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, |
| 1240 |
{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, |
| 1241 |
|
| 1242 |
{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, |
| 1243 |
|
| 1244 |
{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, |
| 1245 |
|
| 1246 |
{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, |
| 1247 |
{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } }, |
| 1248 |
|
| 1249 |
{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, |
| 1250 |
{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } }, |
| 1251 |
|
| 1252 |
{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, |
| 1253 |
{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, |
| 1254 |
|
| 1255 |
{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, |
| 1256 |
{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, |
| 1257 |
|
| 1258 |
{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, |
| 1259 |
{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } }, |
| 1260 |
{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } }, |
| 1261 |
{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } }, |
| 1262 |
|
| 1263 |
{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, |
| 1264 |
{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } }, |
| 1265 |
{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } }, |
| 1266 |
|
| 1267 |
{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, |
| 1268 |
{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, |
| 1269 |
{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, |
| 1270 |
{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, |
| 1271 |
{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, |
| 1272 |
{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, |
| 1273 |
{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, |
| 1274 |
{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, |
| 1275 |
{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, |
| 1276 |
{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, |
| 1277 |
{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, |
| 1278 |
{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, |
| 1279 |
{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, |
| 1280 |
{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, |
| 1281 |
{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, |
| 1282 |
{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, |
| 1283 |
{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, |
| 1284 |
{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, |
| 1285 |
{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, |
| 1286 |
{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, |
| 1287 |
{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, |
| 1288 |
{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, |
| 1289 |
{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, |
| 1290 |
{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, |
| 1291 |
{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1292 |
{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1293 |
{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1294 |
{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1295 |
{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1296 |
{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1297 |
{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1298 |
{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1299 |
{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1300 |
{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1301 |
{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1302 |
{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1303 |
{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1304 |
{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1305 |
{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1306 |
{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1307 |
{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1308 |
{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1309 |
{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1310 |
{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1311 |
{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1312 |
{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1313 |
{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1314 |
{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1315 |
{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1316 |
{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1317 |
{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1318 |
{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1319 |
{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1320 |
{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1321 |
{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1322 |
{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1323 |
{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1324 |
{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1325 |
{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1326 |
{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1327 |
{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1328 |
{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1329 |
{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1330 |
{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1331 |
{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1332 |
{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1333 |
{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1334 |
{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1335 |
{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1336 |
{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1337 |
{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1338 |
{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1339 |
{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1340 |
{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1341 |
{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
| 1342 |
{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1343 |
{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1344 |
{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
| 1345 |
{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1346 |
{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1347 |
{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
| 1348 |
{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1349 |
{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1350 |
{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
| 1351 |
{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1352 |
{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1353 |
{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1354 |
{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1355 |
{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1356 |
{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1357 |
{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1358 |
{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1359 |
{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1360 |
{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1361 |
{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1362 |
{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1363 |
{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1364 |
{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1365 |
{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1366 |
{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1367 |
{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1368 |
{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1369 |
{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1370 |
{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1371 |
{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1372 |
{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1373 |
{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1374 |
{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1375 |
{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1376 |
{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1377 |
{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1378 |
{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1379 |
{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1380 |
{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1381 |
{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1382 |
{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1383 |
{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1384 |
{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1385 |
{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1386 |
{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1387 |
{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1388 |
{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1389 |
{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1390 |
{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1391 |
{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1392 |
{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1393 |
{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1394 |
{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1395 |
{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1396 |
{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1397 |
{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1398 |
{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1399 |
{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1400 |
{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1401 |
{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1402 |
{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1403 |
{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1404 |
{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1405 |
{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1406 |
{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1407 |
{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1408 |
{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1409 |
{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1410 |
{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1411 |
{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1412 |
{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1413 |
{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, |
| 1414 |
{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1415 |
{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1416 |
{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, |
| 1417 |
{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1418 |
{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1419 |
{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1420 |
{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1421 |
{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1422 |
{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, |
| 1423 |
{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1424 |
{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1425 |
{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
| 1426 |
{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, |
| 1427 |
{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, |
| 1428 |
{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, |
| 1429 |
{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1430 |
{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1431 |
{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
| 1432 |
{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, |
| 1433 |
{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, |
| 1434 |
{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, |
| 1435 |
{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
| 1436 |
{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
| 1437 |
{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1438 |
{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
| 1439 |
{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
| 1440 |
{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1441 |
{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
| 1442 |
{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
| 1443 |
{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1444 |
{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
| 1445 |
{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
| 1446 |
{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1447 |
{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
| 1448 |
{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
| 1449 |
{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1450 |
{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
| 1451 |
{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
| 1452 |
{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1453 |
{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
| 1454 |
{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
| 1455 |
{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1456 |
{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
| 1457 |
{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
| 1458 |
{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1459 |
{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
| 1460 |
{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
| 1461 |
{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, |
| 1462 |
{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
| 1463 |
{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
| 1464 |
{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, |
| 1465 |
{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
| 1466 |
{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
| 1467 |
{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
| 1468 |
{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
| 1469 |
{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
| 1470 |
{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
| 1471 |
{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
| 1472 |
{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
| 1473 |
{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, |
| 1474 |
{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, |
| 1475 |
{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, |
| 1476 |
{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, |
| 1477 |
{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
| 1478 |
{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
| 1479 |
{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
| 1480 |
{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, |
| 1481 |
{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, |
| 1482 |
{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, |
| 1483 |
{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
| 1484 |
{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
| 1485 |
{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1486 |
{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
| 1487 |
{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
| 1488 |
{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1489 |
{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
| 1490 |
{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
| 1491 |
{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1492 |
{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
| 1493 |
{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
| 1494 |
{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1495 |
{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
| 1496 |
{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
| 1497 |
{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1498 |
{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, |
| 1499 |
{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, |
| 1500 |
{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, |
| 1501 |
{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
| 1502 |
{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
| 1503 |
{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1504 |
{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, |
| 1505 |
{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, |
| 1506 |
{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, |
| 1507 |
{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, |
| 1508 |
{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, |
| 1509 |
{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, |
| 1510 |
{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, |
| 1511 |
{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, |
| 1512 |
{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, |
| 1513 |
{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, |
| 1514 |
{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, |
| 1515 |
{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, |
| 1516 |
{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, |
| 1517 |
{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, |
| 1518 |
{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, |
| 1519 |
|
| 1520 |
{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, |
| 1521 |
|
| 1522 |
{ "b", B(18,0,0), B_MASK, COM, { LI } }, |
| 1523 |
{ "bl", B(18,0,1), B_MASK, COM, { LI } }, |
| 1524 |
{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, |
| 1525 |
{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, |
| 1526 |
|
| 1527 |
{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, |
| 1528 |
|
| 1529 |
{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1530 |
{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1531 |
{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1532 |
{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
| 1533 |
{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
| 1534 |
{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
| 1535 |
{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
| 1536 |
{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1537 |
{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
| 1538 |
{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
| 1539 |
{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
| 1540 |
{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
| 1541 |
{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1542 |
{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
| 1543 |
{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
| 1544 |
{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
| 1545 |
{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, |
| 1546 |
{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, |
| 1547 |
{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
| 1548 |
{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, |
| 1549 |
{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
| 1550 |
{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, |
| 1551 |
{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1552 |
{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1553 |
{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1554 |
{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1555 |
{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1556 |
{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1557 |
{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1558 |
{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1559 |
{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1560 |
{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1561 |
{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1562 |
{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1563 |
{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1564 |
{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1565 |
{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1566 |
{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1567 |
{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1568 |
{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1569 |
{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1570 |
{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1571 |
{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1572 |
{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1573 |
{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1574 |
{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1575 |
{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1576 |
{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1577 |
{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1578 |
{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1579 |
{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1580 |
{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1581 |
{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1582 |
{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1583 |
{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1584 |
{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1585 |
{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1586 |
{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1587 |
{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1588 |
{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1589 |
{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1590 |
{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1591 |
{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1592 |
{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1593 |
{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1594 |
{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1595 |
{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1596 |
{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1597 |
{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1598 |
{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1599 |
{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1600 |
{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1601 |
{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1602 |
{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1603 |
{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1604 |
{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1605 |
{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1606 |
{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1607 |
{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1608 |
{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1609 |
{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1610 |
{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1611 |
{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1612 |
{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1613 |
{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1614 |
{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1615 |
{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1616 |
{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1617 |
{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1618 |
{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1619 |
{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1620 |
{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1621 |
{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1622 |
{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1623 |
{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1624 |
{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1625 |
{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1626 |
{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1627 |
{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1628 |
{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1629 |
{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1630 |
{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1631 |
{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1632 |
{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1633 |
{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1634 |
{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1635 |
{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1636 |
{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1637 |
{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1638 |
{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1639 |
{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1640 |
{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1641 |
{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1642 |
{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1643 |
{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1644 |
{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1645 |
{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1646 |
{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1647 |
{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1648 |
{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1649 |
{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1650 |
{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1651 |
{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1652 |
{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1653 |
{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1654 |
{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1655 |
{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1656 |
{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1657 |
{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1658 |
{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1659 |
{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1660 |
{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1661 |
{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1662 |
{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1663 |
{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1664 |
{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1665 |
{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1666 |
{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1667 |
{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1668 |
{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1669 |
{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1670 |
{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1671 |
{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1672 |
{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1673 |
{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1674 |
{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1675 |
{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1676 |
{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1677 |
{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1678 |
{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1679 |
{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1680 |
{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, |
| 1681 |
{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1682 |
{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1683 |
{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1684 |
{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1685 |
{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1686 |
{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1687 |
{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1688 |
{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1689 |
{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1690 |
{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1691 |
{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1692 |
{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1693 |
{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1694 |
{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, |
| 1695 |
{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1696 |
{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1697 |
{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1698 |
{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, |
| 1699 |
{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1700 |
{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1701 |
{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1702 |
{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1703 |
{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1704 |
{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1705 |
{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
| 1706 |
{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, |
| 1707 |
{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1708 |
{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1709 |
{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1710 |
{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1711 |
{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1712 |
{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1713 |
{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1714 |
{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1715 |
{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1716 |
{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1717 |
{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1718 |
{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1719 |
{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1720 |
{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1721 |
{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1722 |
{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1723 |
{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1724 |
{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1725 |
{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1726 |
{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1727 |
{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1728 |
{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1729 |
{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1730 |
{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1731 |
{ "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } }, |
| 1732 |
{ "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } }, |
| 1733 |
{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 1734 |
{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 1735 |
{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 1736 |
{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 1737 |
{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, |
| 1738 |
{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, |
| 1739 |
|
| 1740 |
{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, |
| 1741 |
{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, |
| 1742 |
// XXX |
| 1743 |
{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, |
| 1744 |
|
| 1745 |
|
| 1746 |
{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, |
| 1747 |
|
| 1748 |
{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, |
| 1749 |
|
| 1750 |
{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, |
| 1751 |
|
| 1752 |
{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, |
| 1753 |
{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, |
| 1754 |
|
| 1755 |
{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, |
| 1756 |
|
| 1757 |
{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, |
| 1758 |
|
| 1759 |
{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, |
| 1760 |
{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, |
| 1761 |
|
| 1762 |
{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, |
| 1763 |
|
| 1764 |
{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, |
| 1765 |
{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, |
| 1766 |
|
| 1767 |
{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, |
| 1768 |
{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, |
| 1769 |
{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1770 |
{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1771 |
{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1772 |
{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1773 |
{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1774 |
{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1775 |
{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1776 |
{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1777 |
{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1778 |
{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1779 |
{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1780 |
{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1781 |
{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1782 |
{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1783 |
{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1784 |
{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1785 |
{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1786 |
{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1787 |
{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1788 |
{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1789 |
{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1790 |
{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1791 |
{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1792 |
{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1793 |
{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1794 |
{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1795 |
{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1796 |
{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1797 |
{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1798 |
{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1799 |
{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1800 |
{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1801 |
{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1802 |
{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1803 |
{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1804 |
{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1805 |
{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1806 |
{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1807 |
{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1808 |
{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1809 |
{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1810 |
{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1811 |
{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1812 |
{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1813 |
{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1814 |
{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1815 |
{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1816 |
{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1817 |
{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1818 |
{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1819 |
{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1820 |
{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1821 |
{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1822 |
{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1823 |
{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1824 |
{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1825 |
{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1826 |
{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1827 |
{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1828 |
{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1829 |
{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1830 |
{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1831 |
{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1832 |
{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1833 |
{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1834 |
{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1835 |
{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1836 |
{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1837 |
{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1838 |
{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1839 |
{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1840 |
{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1841 |
{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1842 |
{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1843 |
{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1844 |
{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1845 |
{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1846 |
{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1847 |
{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1848 |
{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1849 |
{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1850 |
{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1851 |
{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1852 |
{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1853 |
{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1854 |
{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1855 |
{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1856 |
{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1857 |
{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1858 |
{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1859 |
{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1860 |
{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1861 |
{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1862 |
{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1863 |
{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1864 |
{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1865 |
{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1866 |
{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1867 |
{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1868 |
{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1869 |
{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1870 |
{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1871 |
{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1872 |
{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1873 |
{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1874 |
{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1875 |
{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1876 |
{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1877 |
{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1878 |
{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1879 |
{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1880 |
{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1881 |
{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1882 |
{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1883 |
{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1884 |
{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, |
| 1885 |
{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1886 |
{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, |
| 1887 |
{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1888 |
{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, |
| 1889 |
{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1890 |
{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1891 |
{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1892 |
{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
| 1893 |
{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
| 1894 |
{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1895 |
{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1896 |
{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1897 |
{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
| 1898 |
{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
| 1899 |
{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1900 |
{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1901 |
{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1902 |
{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
| 1903 |
{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, |
| 1904 |
{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, |
| 1905 |
{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1906 |
{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, |
| 1907 |
{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
| 1908 |
{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, |
| 1909 |
{ "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } }, |
| 1910 |
{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 1911 |
{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 1912 |
{ "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } }, |
| 1913 |
{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 1914 |
{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, |
| 1915 |
{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, |
| 1916 |
{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, |
| 1917 |
{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } }, |
| 1918 |
{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } }, |
| 1919 |
|
| 1920 |
{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
| 1921 |
|
| 1922 |
{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
| 1923 |
|
| 1924 |
{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, |
| 1925 |
{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, |
| 1926 |
{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
| 1927 |
{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, |
| 1928 |
{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, |
| 1929 |
{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, |
| 1930 |
|
| 1931 |
{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, |
| 1932 |
{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, |
| 1933 |
{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, |
| 1934 |
{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, |
| 1935 |
|
| 1936 |
{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, |
| 1937 |
{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, |
| 1938 |
|
| 1939 |
{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, |
| 1940 |
|
| 1941 |
{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, |
| 1942 |
|
| 1943 |
{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, |
| 1944 |
|
| 1945 |
{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, |
| 1946 |
|
| 1947 |
{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, |
| 1948 |
|
| 1949 |
{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, |
| 1950 |
{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, |
| 1951 |
|
| 1952 |
{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1953 |
{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1954 |
{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1955 |
{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1956 |
{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1957 |
{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1958 |
{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1959 |
{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1960 |
{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1961 |
{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1962 |
{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1963 |
{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1964 |
{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1965 |
{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, |
| 1966 |
{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, |
| 1967 |
{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, |
| 1968 |
|
| 1969 |
{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 1970 |
{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, |
| 1971 |
{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 1972 |
{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, |
| 1973 |
{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 1974 |
{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, |
| 1975 |
{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 1976 |
{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, |
| 1977 |
|
| 1978 |
{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 1979 |
{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 1980 |
{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 1981 |
{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 1982 |
|
| 1983 |
{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
| 1984 |
{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
| 1985 |
|
| 1986 |
{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } }, |
| 1987 |
|
| 1988 |
{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, |
| 1989 |
|
| 1990 |
{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } }, |
| 1991 |
|
| 1992 |
{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, |
| 1993 |
{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, |
| 1994 |
|
| 1995 |
{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, |
| 1996 |
{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, |
| 1997 |
|
| 1998 |
{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, |
| 1999 |
{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, |
| 2000 |
|
| 2001 |
{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, |
| 2002 |
{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, |
| 2003 |
|
| 2004 |
{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
| 2005 |
{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, |
| 2006 |
{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
| 2007 |
{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, |
| 2008 |
{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
| 2009 |
{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, |
| 2010 |
{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
| 2011 |
{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, |
| 2012 |
|
| 2013 |
{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, |
| 2014 |
|
| 2015 |
{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, |
| 2016 |
|
| 2017 |
{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, |
| 2018 |
|
| 2019 |
{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, |
| 2020 |
{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, |
| 2021 |
|
| 2022 |
{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
| 2023 |
{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
| 2024 |
|
| 2025 |
{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, |
| 2026 |
|
| 2027 |
{ "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, |
| 2028 |
|
| 2029 |
{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } }, |
| 2030 |
|
| 2031 |
{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, |
| 2032 |
{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, |
| 2033 |
{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, |
| 2034 |
{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, |
| 2035 |
|
| 2036 |
{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, |
| 2037 |
|
| 2038 |
{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, |
| 2039 |
{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, |
| 2040 |
{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, |
| 2041 |
{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, |
| 2042 |
|
| 2043 |
{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2044 |
{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2045 |
{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2046 |
{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2047 |
|
| 2048 |
{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2049 |
{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2050 |
{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2051 |
{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2052 |
|
| 2053 |
{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }}, |
| 2054 |
{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, |
| 2055 |
|
| 2056 |
{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, |
| 2057 |
|
| 2058 |
{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, |
| 2059 |
|
| 2060 |
{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } }, |
| 2061 |
|
| 2062 |
{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, |
| 2063 |
|
| 2064 |
{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2065 |
{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2066 |
{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2067 |
{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2068 |
|
| 2069 |
{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2070 |
{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2071 |
{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2072 |
{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2073 |
|
| 2074 |
{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, |
| 2075 |
|
| 2076 |
{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } }, |
| 2077 |
|
| 2078 |
{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } }, |
| 2079 |
|
| 2080 |
{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2081 |
{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2082 |
{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2083 |
{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2084 |
|
| 2085 |
{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2086 |
{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2087 |
{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2088 |
{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, |
| 2089 |
|
| 2090 |
{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2091 |
{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2092 |
{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2093 |
{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2094 |
|
| 2095 |
{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, |
| 2096 |
{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, |
| 2097 |
|
| 2098 |
{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } }, |
| 2099 |
|
| 2100 |
{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, |
| 2101 |
|
| 2102 |
{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2103 |
{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2104 |
{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2105 |
{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, |
| 2106 |
|
| 2107 |
{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } }, |
| 2108 |
|
| 2109 |
{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } }, |
| 2110 |
|
| 2111 |
{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, |
| 2112 |
{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, |
| 2113 |
|
| 2114 |
{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, |
| 2115 |
|
| 2116 |
{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, |
| 2117 |
|
| 2118 |
{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, |
| 2119 |
|
| 2120 |
{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, |
| 2121 |
{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, |
| 2122 |
|
| 2123 |
{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, |
| 2124 |
{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, |
| 2125 |
{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, |
| 2126 |
{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, |
| 2127 |
{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, |
| 2128 |
{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, |
| 2129 |
{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, |
| 2130 |
{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, |
| 2131 |
{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, |
| 2132 |
{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, |
| 2133 |
{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, |
| 2134 |
{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, |
| 2135 |
{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, |
| 2136 |
{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, |
| 2137 |
{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, |
| 2138 |
{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, |
| 2139 |
{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, |
| 2140 |
{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, |
| 2141 |
{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, |
| 2142 |
{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, |
| 2143 |
{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, |
| 2144 |
{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
| 2145 |
{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
| 2146 |
{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
| 2147 |
{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
| 2148 |
{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, |
| 2149 |
{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, |
| 2150 |
{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, |
| 2151 |
{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, |
| 2152 |
{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, |
| 2153 |
{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, |
| 2154 |
{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, |
| 2155 |
{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, |
| 2156 |
{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, |
| 2157 |
{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, |
| 2158 |
{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, |
| 2159 |
{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, |
| 2160 |
{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, |
| 2161 |
{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, |
| 2162 |
{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, |
| 2163 |
{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, |
| 2164 |
{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, |
| 2165 |
{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, |
| 2166 |
{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, |
| 2167 |
{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, |
| 2168 |
|
| 2169 |
{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } }, |
| 2170 |
|
| 2171 |
{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
| 2172 |
{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
| 2173 |
|
| 2174 |
{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } }, |
| 2175 |
|
| 2176 |
{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
| 2177 |
{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, |
| 2178 |
|
| 2179 |
{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, |
| 2180 |
|
| 2181 |
{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, |
| 2182 |
{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, |
| 2183 |
{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, |
| 2184 |
|
| 2185 |
{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, |
| 2186 |
|
| 2187 |
{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } }, |
| 2188 |
|
| 2189 |
{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, |
| 2190 |
{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, |
| 2191 |
|
| 2192 |
{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, |
| 2193 |
|
| 2194 |
{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, |
| 2195 |
|
| 2196 |
{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, |
| 2197 |
{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, |
| 2198 |
{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, |
| 2199 |
{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, |
| 2200 |
|
| 2201 |
{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
| 2202 |
{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
| 2203 |
{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
| 2204 |
{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
| 2205 |
|
| 2206 |
{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, |
| 2207 |
{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, |
| 2208 |
{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, |
| 2209 |
{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, |
| 2210 |
{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, |
| 2211 |
{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, |
| 2212 |
{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, |
| 2213 |
{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, |
| 2214 |
{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, |
| 2215 |
{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, |
| 2216 |
{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, |
| 2217 |
{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } }, |
| 2218 |
{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } }, |
| 2219 |
{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } }, |
| 2220 |
{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } }, |
| 2221 |
{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } }, |
| 2222 |
{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } }, |
| 2223 |
{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, |
| 2224 |
{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, |
| 2225 |
{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, |
| 2226 |
{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
| 2227 |
{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
| 2228 |
{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
| 2229 |
{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
| 2230 |
{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } }, |
| 2231 |
{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } }, |
| 2232 |
{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } }, |
| 2233 |
{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } }, |
| 2234 |
{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } }, |
| 2235 |
{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } }, |
| 2236 |
{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } }, |
| 2237 |
{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } }, |
| 2238 |
{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } }, |
| 2239 |
{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } }, |
| 2240 |
{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } }, |
| 2241 |
{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } }, |
| 2242 |
{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } }, |
| 2243 |
{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } }, |
| 2244 |
{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } }, |
| 2245 |
{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } }, |
| 2246 |
{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } }, |
| 2247 |
{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } }, |
| 2248 |
{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } }, |
| 2249 |
{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, |
| 2250 |
|
| 2251 |
{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, |
| 2252 |
|
| 2253 |
{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, |
| 2254 |
{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, |
| 2255 |
|
| 2256 |
{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
| 2257 |
{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
| 2258 |
{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
| 2259 |
{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
| 2260 |
|
| 2261 |
{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, |
| 2262 |
|
| 2263 |
{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, |
| 2264 |
|
| 2265 |
{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } }, |
| 2266 |
|
| 2267 |
{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } }, |
| 2268 |
|
| 2269 |
{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } }, |
| 2270 |
|
| 2271 |
{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, |
| 2272 |
{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, |
| 2273 |
|
| 2274 |
{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, |
| 2275 |
|
| 2276 |
{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, |
| 2277 |
|
| 2278 |
{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, |
| 2279 |
|
| 2280 |
{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } }, |
| 2281 |
|
| 2282 |
{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } }, |
| 2283 |
{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, |
| 2284 |
|
| 2285 |
{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } }, |
| 2286 |
|
| 2287 |
{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, |
| 2288 |
|
| 2289 |
{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, |
| 2290 |
|
| 2291 |
{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } }, |
| 2292 |
|
| 2293 |
{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } }, |
| 2294 |
|
| 2295 |
{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } }, |
| 2296 |
|
| 2297 |
{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, |
| 2298 |
|
| 2299 |
{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } }, |
| 2300 |
|
| 2301 |
{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } }, |
| 2302 |
|
| 2303 |
{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, |
| 2304 |
|
| 2305 |
{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } }, |
| 2306 |
|
| 2307 |
{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, |
| 2308 |
{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, |
| 2309 |
|
| 2310 |
{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, |
| 2311 |
{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, |
| 2312 |
|
| 2313 |
{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, |
| 2314 |
{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, |
| 2315 |
|
| 2316 |
{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, |
| 2317 |
|
| 2318 |
{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } }, |
| 2319 |
|
| 2320 |
{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, |
| 2321 |
{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, |
| 2322 |
|
| 2323 |
{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, |
| 2324 |
{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, |
| 2325 |
|
| 2326 |
{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, |
| 2327 |
|
| 2328 |
{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, |
| 2329 |
|
| 2330 |
{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, |
| 2331 |
|
| 2332 |
{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, |
| 2333 |
|
| 2334 |
{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, |
| 2335 |
{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, |
| 2336 |
|
| 2337 |
{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, |
| 2338 |
{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, |
| 2339 |
{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, |
| 2340 |
{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, |
| 2341 |
{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, |
| 2342 |
{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, |
| 2343 |
{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, |
| 2344 |
{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, |
| 2345 |
{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, |
| 2346 |
{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, |
| 2347 |
{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, |
| 2348 |
{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, |
| 2349 |
|
| 2350 |
{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } }, |
| 2351 |
|
| 2352 |
{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, |
| 2353 |
|
| 2354 |
{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } }, |
| 2355 |
|
| 2356 |
{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, |
| 2357 |
|
| 2358 |
{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } }, |
| 2359 |
|
| 2360 |
{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, |
| 2361 |
|
| 2362 |
{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } }, |
| 2363 |
|
| 2364 |
{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, |
| 2365 |
|
| 2366 |
{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } }, |
| 2367 |
|
| 2368 |
{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, |
| 2369 |
|
| 2370 |
{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } }, |
| 2371 |
|
| 2372 |
{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, |
| 2373 |
|
| 2374 |
{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } }, |
| 2375 |
|
| 2376 |
{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, |
| 2377 |
|
| 2378 |
{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, |
| 2379 |
|
| 2380 |
{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } }, |
| 2381 |
|
| 2382 |
{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } }, |
| 2383 |
|
| 2384 |
{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, |
| 2385 |
|
| 2386 |
{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } }, |
| 2387 |
|
| 2388 |
{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, |
| 2389 |
|
| 2390 |
{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } }, |
| 2391 |
|
| 2392 |
{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, |
| 2393 |
|
| 2394 |
{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } }, |
| 2395 |
|
| 2396 |
{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, |
| 2397 |
|
| 2398 |
{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
| 2399 |
{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
| 2400 |
|
| 2401 |
{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
| 2402 |
{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
| 2403 |
|
| 2404 |
{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
| 2405 |
{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
| 2406 |
|
| 2407 |
{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
| 2408 |
{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
| 2409 |
|
| 2410 |
{ "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
| 2411 |
{ "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
| 2412 |
|
| 2413 |
{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
| 2414 |
{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
| 2415 |
|
| 2416 |
{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2417 |
{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2418 |
|
| 2419 |
{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2420 |
{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2421 |
|
| 2422 |
{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2423 |
{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2424 |
|
| 2425 |
{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2426 |
{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2427 |
|
| 2428 |
{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, |
| 2429 |
|
| 2430 |
{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, |
| 2431 |
{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, |
| 2432 |
|
| 2433 |
{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, |
| 2434 |
{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, |
| 2435 |
|
| 2436 |
{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, |
| 2437 |
{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, |
| 2438 |
|
| 2439 |
{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
| 2440 |
{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
| 2441 |
|
| 2442 |
{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
| 2443 |
{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
| 2444 |
|
| 2445 |
{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
| 2446 |
{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, |
| 2447 |
|
| 2448 |
{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, |
| 2449 |
{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, |
| 2450 |
|
| 2451 |
{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2452 |
{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
| 2453 |
|
| 2454 |
{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, |
| 2455 |
{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, |
| 2456 |
|
| 2457 |
{ "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
| 2458 |
{ "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
| 2459 |
|
| 2460 |
{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
| 2461 |
{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
| 2462 |
|
| 2463 |
{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
| 2464 |
{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
| 2465 |
|
| 2466 |
{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
| 2467 |
{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
| 2468 |
|
| 2469 |
{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
| 2470 |
{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, |
| 2471 |
|
| 2472 |
{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, |
| 2473 |
|
| 2474 |
{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, |
| 2475 |
{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, |
| 2476 |
|
| 2477 |
{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, |
| 2478 |
{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, |
| 2479 |
|
| 2480 |
{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, |
| 2481 |
|
| 2482 |
{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, |
| 2483 |
{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, |
| 2484 |
|
| 2485 |
{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, |
| 2486 |
{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, |
| 2487 |
|
| 2488 |
{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, |
| 2489 |
{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, |
| 2490 |
|
| 2491 |
{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, |
| 2492 |
{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, |
| 2493 |
|
| 2494 |
{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, |
| 2495 |
{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, |
| 2496 |
|
| 2497 |
{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, |
| 2498 |
{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, |
| 2499 |
|
| 2500 |
{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, |
| 2501 |
{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, |
| 2502 |
|
| 2503 |
}; |
| 2504 |
|
| 2505 |
const int powerpc_num_opcodes = |
| 2506 |
sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); |
| 2507 |
|
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