/[pearpc]/src/cpu/cpu_jitc_x86/ppc_exc.cc
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Annotation of /src/cpu/cpu_jitc_x86/ppc_exc.cc

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Revision 1 - (hide annotations)
Wed Sep 5 17:11:21 2007 UTC (13 years, 1 month ago) by dpavlin
File size: 2919 byte(s)
import upstream CVS
1 dpavlin 1 /*
2     * PearPC
3     * ppc_exc.cc
4     *
5     * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net)
6     * Copyright (C) 2004 Daniel Foesch (dfoesch@cs.nmsu.edu)
7     *
8     * This program is free software; you can redistribute it and/or modify
9     * it under the terms of the GNU General Public License version 2 as
10     * published by the Free Software Foundation.
11     *
12     * This program is distributed in the hope that it will be useful,
13     * but WITHOUT ANY WARRANTY; without even the implied warranty of
14     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15     * GNU General Public License for more details.
16     *
17     * You should have received a copy of the GNU General Public License
18     * along with this program; if not, write to the Free Software
19     * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20     */
21    
22     #include "tools/snprintf.h"
23     #include "debug/tracers.h"
24     #include "info.h"
25     #include "ppc_cpu.h"
26     #include "ppc_exc.h"
27     #include "ppc_mmu.h"
28    
29     /*
30     * .247
31     */
32     bool FASTCALL ppc_exception(uint32 type, uint32 flags, uint32 a)
33     {
34     if (type != PPC_EXC_DEC) PPC_EXC_TRACE("@%08x: type = %08x (%08x, %08x)\n", gCPU.pc, type, flags, a);
35     switch (type) {
36     case PPC_EXC_DSI: { // .271
37     gCPU.srr[0] = gCPU.pc;
38     gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
39     gCPU.dar = a;
40     gCPU.dsisr = flags;
41     break;
42     }
43     case PPC_EXC_ISI: { // .274
44     if (gCPU.pc == 0) {
45     PPC_EXC_WARN("pc == 0 in ISI\n");
46     SINGLESTEP("");
47     }
48     gCPU.srr[0] = gCPU.pc;
49     gCPU.srr[1] = (gCPU.msr & 0x87c0ffff) | flags;
50     break;
51     }
52     case PPC_EXC_DEC: { // .284
53     gCPU.srr[0] = gCPU.pc;
54     gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
55     break;
56     }
57     case PPC_EXC_EXT_INT: {
58     gCPU.srr[0] = gCPU.pc;
59     gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
60     break;
61     }
62     case PPC_EXC_SC: { // .285
63     gCPU.srr[0] = gCPU.npc;
64     gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
65     break;
66     }
67     case PPC_EXC_NO_FPU: { // .284
68     gCPU.srr[0] = gCPU.pc;
69     gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
70     break;
71     }
72     case PPC_EXC_NO_VEC: {
73     gCPU.srr[0] = gCPU.pc;
74     gCPU.srr[1] = gCPU.msr & 0x0000ff73;
75     break;
76     }
77     case PPC_EXC_PROGRAM: { // .283
78     if (flags & PPC_EXC_PROGRAM_NEXT) {
79     gCPU.srr[0] = gCPU.npc;
80     } else {
81     gCPU.srr[0] = gCPU.pc;
82     }
83     gCPU.srr[1] = (gCPU.msr & 0x87c0ffff) | flags;
84     break;
85     }
86     case PPC_EXC_FLOAT_ASSIST: { // .288
87     gCPU.srr[0] = gCPU.pc;
88     gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
89     break;
90     }
91     case PPC_EXC_MACHINE_CHECK: { // .270
92     if (!(gCPU.msr & MSR_ME)) {
93     PPC_EXC_ERR("machine check exception and MSR[ME]=0.\n");
94     }
95     gCPU.srr[0] = gCPU.pc;
96     gCPU.srr[1] = (gCPU.msr & 0x87c0ffff) | MSR_RI;
97     break;
98     }
99     case PPC_EXC_TRACE2: { // .286
100     gCPU.srr[0] = gCPU.pc;
101     gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
102     break;
103     }
104     default:
105     PPC_EXC_ERR("unknown\n");
106     return false;
107     }
108     ppc_mmu_tlb_invalidate();
109     gCPU.msr = 0;
110     gCPU.npc = type;
111     return true;
112     }
113    
114     void ppc_cpu_raise_ext_exception()
115     {
116     ppc_cpu_atomic_raise_ext_exception();
117     }
118    
119     void ppc_cpu_cancel_ext_exception()
120     {
121     ppc_cpu_atomic_cancel_ext_exception();
122     }

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