/[pearpc]/src/cpu/cpu_generic/ppc_exc.cc
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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Contents of /src/cpu/cpu_generic/ppc_exc.cc

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Revision 1 - (show annotations)
Wed Sep 5 17:11:21 2007 UTC (12 years, 2 months ago) by dpavlin
File size: 3084 byte(s)
import upstream CVS
1 /*
2 * PearPC
3 * ppc_exc.cc
4 *
5 * Copyright (C) 2003 Sebastian Biallas (sb@biallas.net)
6 * Copyright (C) 2004 Daniel Foesch (dfoesch@cs.nmsu.edu)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22 /* Pages marked: v.???
23 * From: IBM PowerPC MicroProcessor Family: Altivec(tm) Technology...
24 * Programming Environments Manual
25 */
26
27 #include "tools/snprintf.h"
28 #include "debug/tracers.h"
29 #include "cpu/debug.h"
30 #include "info.h"
31 #include "ppc_cpu.h"
32 #include "ppc_exc.h"
33 #include "ppc_mmu.h"
34
35 /*
36 * .247
37 */
38 bool FASTCALL ppc_exception(uint32 type, uint32 flags, uint32 a)
39 {
40 if (type != PPC_EXC_DEC) PPC_EXC_TRACE("@%08x: type = %08x (%08x, %08x)\n", gCPU.pc, type, flags, a);
41 switch (type) {
42 case PPC_EXC_DSI: { // .271
43 gCPU.srr[0] = gCPU.pc;
44 gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
45 gCPU.dar = a;
46 gCPU.dsisr = flags;
47 break;
48 }
49 case PPC_EXC_ISI: { // .274
50 if (gCPU.pc == 0) {
51 PPC_EXC_WARN("pc == 0 in ISI\n");
52 SINGLESTEP("");
53 }
54 gCPU.srr[0] = gCPU.pc;
55 gCPU.srr[1] = (gCPU.msr & 0x87c0ffff) | flags;
56 break;
57 }
58 case PPC_EXC_DEC: { // .284
59 gCPU.srr[0] = gCPU.pc;
60 gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
61 break;
62 }
63 case PPC_EXC_EXT_INT: {
64 gCPU.srr[0] = gCPU.pc;
65 gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
66 break;
67 }
68 case PPC_EXC_SC: { // .285
69 gCPU.srr[0] = gCPU.npc;
70 gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
71 break;
72 }
73 case PPC_EXC_NO_FPU: { // .284
74 gCPU.srr[0] = gCPU.pc;
75 gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
76 break;
77 }
78 case PPC_EXC_NO_VEC: { // v.41
79 gCPU.srr[0] = gCPU.pc;
80 gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
81 break;
82 }
83 case PPC_EXC_PROGRAM: { // .283
84 if (flags & PPC_EXC_PROGRAM_NEXT) {
85 gCPU.srr[0] = gCPU.npc;
86 } else {
87 gCPU.srr[0] = gCPU.pc;
88 }
89 gCPU.srr[1] = (gCPU.msr & 0x87c0ffff) | flags;
90 break;
91 }
92 case PPC_EXC_FLOAT_ASSIST: { // .288
93 gCPU.srr[0] = gCPU.pc;
94 gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
95 break;
96 }
97 case PPC_EXC_MACHINE_CHECK: { // .270
98 if (!(gCPU.msr & MSR_ME)) {
99 PPC_EXC_ERR("machine check exception and MSR[ME]=0.\n");
100 }
101 gCPU.srr[0] = gCPU.pc;
102 gCPU.srr[1] = (gCPU.msr & 0x87c0ffff) | MSR_RI;
103 break;
104 }
105 case PPC_EXC_TRACE2: { // .286
106 gCPU.srr[0] = gCPU.pc;
107 gCPU.srr[1] = gCPU.msr & 0x87c0ffff;
108 break;
109 }
110 default:
111 PPC_EXC_ERR("unknown\n");
112 return false;
113 }
114 ppc_mmu_tlb_invalidate();
115 gCPU.msr = 0;
116 gCPU.npc = type;
117 return true;
118 }
119
120 void ppc_cpu_raise_ext_exception()
121 {
122 ppc_cpu_atomic_raise_ext_exception();
123 }
124
125 void ppc_cpu_cancel_ext_exception()
126 {
127 ppc_cpu_atomic_cancel_ext_exception();
128 }

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