/[pearpc]/src/cpu/common.h
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Contents of /src/cpu/common.h

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Revision 2 - (show annotations)
Wed Sep 5 17:16:00 2007 UTC (12 years, 9 months ago) by dpavlin
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make dist in CVS tree forgot this one
1 /*
2 * PearPC
3 * common.h
4 *
5 * Copyright (C) 2003-2006 Sebastian Biallas (sb@biallas.net)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #ifndef __CPU_COMMON_H__
22 #define __CPU_COMMON_H__
23
24 #include <stddef.h>
25 #include "system/types.h"
26
27 typedef union Vector_t {
28 uint64 d[2];
29 sint64 sd[2];
30 float f[4];
31 uint32 w[4];
32 sint32 sw[4];
33 uint16 h[8];
34 sint16 sh[8];
35 uint8 b[16];
36 sint8 sb[16];
37 } Vector_t;
38
39 /*
40 cr: .67
41 0- 3 cr0
42 4- 7 cr1
43 8-11 cr2
44 12-15 cr3
45 16-19 cr4
46 20-23 cr5
47 24-27 cr6
48 28-31 cr7
49 */
50
51 #define CR_CR0(v) ((v)>>28)
52 #define CR_CR1(v) (((v)>>24)&0xf)
53 #define CR_CRx(v, x) (((v)>>(4*(7-(x))))&0xf)
54
55 /*
56 cr0 bits: .68
57 lt
58 gt
59 eq
60 so
61 */
62
63 #define CR_CR0_LT (1<<31)
64 #define CR_CR0_GT (1<<30)
65 #define CR_CR0_EQ (1<<29)
66 #define CR_CR0_SO (1<<28)
67
68 /*
69 cr1 bits: .68
70 4 Floating-point exception (FX)
71 5 Floating-point enabled exception (FEX)
72 6 Floating-point invalid exception (VX)
73 7 Floating-point overflow exception (OX)
74 */
75
76 #define CR_CR1_FX (1<<27)
77 #define CR_CR1_FEX (1<<26)
78 #define CR_CR1_VX (1<<25)
79 #define CR_CR1_OX (1<<24)
80
81 /*
82 FPSCR bits: .70
83
84 */
85
86 #define FPSCR_FX (1<<31)
87 #define FPSCR_FEX (1<<30)
88 #define FPSCR_VX (1<<29)
89 #define FPSCR_OX (1<<28)
90 #define FPSCR_UX (1<<27)
91 #define FPSCR_ZX (1<<26)
92 #define FPSCR_XX (1<<25)
93 #define FPSCR_VXSNAN (1<<24)
94 #define FPSCR_VXISI (1<<23)
95 #define FPSCR_VXIDI (1<<22)
96 #define FPSCR_VXZDZ (1<<21)
97 #define FPSCR_VXIMZ (1<<20)
98 #define FPSCR_VXVC (1<<19)
99 #define FPSCR_FR (1<<18)
100 #define FPSCR_FI (1<<17)
101
102 #define FPSCR_FPRF(v) (((v)>>12)&0x1f)
103
104 #define FPSCR_res0 (1<<11)
105 #define FPSCR_VXSOFT (1<<10)
106 #define FPSCR_VXSQRT (1<<9)
107 #define FPSCR_VXCVI (1<<8)
108 #define FPSCR_VXVE (1<<7)
109 #define FPSCR_VXOE (1<<6)
110 #define FPSCR_VXUE (1<<5)
111 #define FPSCR_VXZE (1<<4)
112 #define FPSCR_VXXE (1<<3)
113 #define FPSCR_VXNI (1<<2)
114 #define FPSCR_RN(v) ((v)&3)
115
116 #define FPSCR_RN_NEAR 0
117 #define FPSCR_RN_ZERO 1
118 #define FPSCR_RN_PINF 2
119 #define FPSCR_RN_MINF 3
120
121 /*
122 VSCR bits:
123 sat = summary saturation
124 nj = non-java floating-point mode
125 */
126 #define VSCR_SAT 1
127 #define VSCR_NJ (1<<16)
128
129 /*
130 xer bits:
131 0 so
132 1 ov
133 2 carry
134 3-24 res
135 25-31 number of bytes for lswx/stswx
136 */
137
138 #define XER_SO (1<<31)
139 #define XER_OV (1<<30)
140 #define XER_CA (1<<29)
141 #define XER_n(v) ((v)&0x7f)
142
143 /*
144 msr: .83
145 0-12 res
146 13 POW power management enabled
147 14 res
148 15 ILE exception little-endian mode
149 16 EE enable external interrupt
150 17 PR privilege level (0=sv)
151 18 FP floating point avail
152 19 ME maschine check exception enable
153 20 FE0 floation point exception mode 0
154 21 SE single step enable
155 22 BE branch trace enable
156 23 FE1 floation point exception mode 1
157 24 res
158 25 IP exception prefix
159 26 IR intruction address translation
160 27 DR data address translation
161 28-29res
162 30 RI recoverable exception
163 31 LE little endian mode
164
165 */
166
167 #define MSR_UNKNOWN (1<<30)
168 #define MSR_UNKNOWN2 (1<<27)
169 #define MSR_VEC (1<<25)
170 #define MSR_KEY (1<<19) // 603e
171 #define MSR_POW (1<<18)
172 #define MSR_TGPR (1<<15) // 603(e)
173 #define MSR_ILE (1<<16)
174 #define MSR_EE (1<<15)
175 #define MSR_PR (1<<14)
176 #define MSR_FP (1<<13)
177 #define MSR_ME (1<<12)
178 #define MSR_FE0 (1<<11)
179 #define MSR_SE (1<<10)
180 #define MSR_BE (1<<9)
181 #define MSR_FE1 (1<<8)
182 #define MSR_IP (1<<6)
183 #define MSR_IR (1<<5)
184 #define MSR_DR (1<<4)
185 #define MSR_PM (1<<2)
186 #define MSR_RI (1<<1)
187 #define MSR_LE (1<<0)
188
189 //#define PPC_CPU_UNSUPPORTED_MSR_BITS (/*MSR_POW|*/MSR_ILE|MSR_BE|MSR_IP|MSR_LE)
190 #define PPC_CPU_UNSUPPORTED_MSR_BITS (~(MSR_POW | MSR_UNKNOWN | MSR_UNKNOWN2 | MSR_VEC | MSR_EE | MSR_PR | MSR_FP | MSR_ME | MSR_FE0 | MSR_SE | MSR_FE1 | MSR_IR | MSR_DR | MSR_RI))
191
192 #define MSR_RFI_SAVE_MASK (0x87c0ff73) // was ff73
193
194 /*
195 BAT Register: .88
196 upper:
197 0-14 BEPI Block effective page index.
198 15-18 res
199 19-29 BL Block length.
200 30 Vs Supervisor mode valid bit.
201 31 Vp User mode valid bit.
202 lower:
203 0-14 BRPN This field is used in conjunction with the BL field to generate highorder bits of the physical address of the block.
204 15-24 res
205 25-28 WIMG Memory/cache access mode bits
206 29 res
207 30-31 PP Protection bits for block.
208
209 BAT Area
210 Length BL Encoding
211 128 Kbytes 000 0000 0000
212 256 Kbytes 000 0000 0001
213 512 Kbytes 000 0000 0011
214 1 Mbyte 000 0000 0111
215 2 Mbytes 000 0000 1111
216 4 Mbytes 000 0001 1111
217 8 Mbytes 000 0011 1111
218 16 Mbytes 000 0111 1111
219 32 Mbytes 000 1111 1111
220 64 Mbytes 001 1111 1111
221 128 Mbytes 011 1111 1111
222 256 Mbytes 111 1111 1111
223 */
224
225 #define BATU_BEPI(v) ((v)&0xfffe0000)
226 #define BATU_BL(v) (((v)&0x1ffc)>>2)
227 #define BATU_Vs (1<<1)
228 #define BATU_Vp (1)
229 #define BATL_BRPN(v) ((v)&0xfffe0000)
230
231 #define BAT_EA_OFFSET(v) ((v)&0x1ffff)
232 #define BAT_EA_11(v) ((v)&0x0ffe0000)
233 #define BAT_EA_4(v) ((v)&0xf0000000)
234
235 /*
236 sdr1: .91
237 0-15 The high-order 16 bits of the 32-bit physical address of the page table
238 16-22 res
239 23-31 Mask for page table address
240 */
241
242 #define SDR1_HTABORG(v) (((v)>>16)&0xffff)
243 #define SDR1_HTABMASK(v) ((v)&0x1ff)
244 #define SDR1_PAGETABLE_BASE(v) ((v)&0xffff)
245
246 /*
247 sr: .94
248 0 T=0:
249 1 Ks sv prot
250 2 Kp user prot
251 3 N No execute
252 4-7 res
253 8-31 VSID Virtual Segment ID
254
255 0 T=1:
256 1 Ks
257 2 Kp
258 3-11 BUID Bus Unit ID
259 12-31 CNTRL_SPEC
260 */
261 #define SR_T (1<<31)
262 #define SR_Ks (1<<30)
263 #define SR_Kp (1<<29)
264 #define SR_N (1<<28)
265 #define SR_VSID(v) ((v)&0xffffff)
266 #define SR_BUID(v) (((v)>>20)&0x1ff)
267 #define SR_CNTRL_SPEC(v) ((v)&0xfffff)
268
269 #define EA_SR(v) (((v)>>28)&0xf)
270 #define EA_PageIndex(v) (((v)>>12)&0xffff)
271 #define EA_Offset(v) ((v)&0xfff)
272 #define EA_API(v) (((v)>>22)&0x3f)
273
274 #define PA_RPN(v) (((v)>>12)&0xfffff)
275 #define PA_Offset(v) ((v)&0xfff)
276
277 /*
278 PTE: .364
279 0 V
280 1-24 VSID
281 25 H
282 26-31 API
283 */
284
285 #define PTE1_V (1<<31)
286 #define PTE1_VSID(v) (((v)>>7)&0xffffff)
287 #define PTE1_H (1<<6)
288 #define PTE1_API(v) ((v)&0x3f)
289
290 #define PTE2_RPN(v) ((v)&0xfffff000)
291 #define PTE2_R (1<<8)
292 #define PTE2_C (1<<7)
293 #define PTE2_WIMG(v) (((v)>>3)&0xf)
294 #define PTE2_PP(v) ((v)&3)
295
296 #define PPC_L1_CACHE_LINE_SIZE 32
297 #define PPC_LG_L1_CACHE_LINE_SIZE 5
298 #define PPC_MAX_L1_COPY_PREFETCH 4
299
300 /*
301 * special registers
302 */
303 #define HID0 1008 /* Checkstop and misc enables */
304 #define HID1 1009 /* Clock configuration */
305 #define IABR 1010 /* Instruction address breakpoint register */
306 #define ICTRL 1011 /* Instruction Cache Control */
307 #define LDSTDB 1012 /* Load/Store Debug */
308 #define DABR 1013 /* Data address breakpoint register */
309 #define MSSCR0 1014 /* Memory subsystem control */
310 #define MSSCR1 1015 /* Memory subsystem debug */
311 #define MSSSR0 1015 /* Memory Subsystem Status */
312 #define LDSTCR 1016 /* Load/Store Status/Control */
313 #define L2CR2 1016 /* L2 Cache control 2 */
314 #define L2CR 1017 /* L2 Cache control */
315 #define L3CR 1018 /* L3 Cache control */
316 #define ICTC 1019 /* I-cache throttling control */
317 #define THRM1 1020 /* Thermal management 1 */
318 #define THRM2 1021 /* Thermal management 2 */
319 #define THRM3 1022 /* Thermal management 3 */
320 #define PIR 1023 /* Processor ID Register */
321
322 //; hid0 bits
323 #define HID0_emcp 0
324 #define HID0_emcpm 0x80000000
325 #define HID0_dbp 1
326 #define HID0_dbpm 0x40000000
327 #define HID0_eba 2
328 #define HID0_ebam 0x20000000
329 #define HID0_ebd 3
330 #define HID0_ebdm 0x10000000
331 #define HID0_sbclk 4
332 #define HID0_sbclkm 0x08000000
333 #define HID0_eclk 6
334 #define HID0_eclkm 0x02000000
335 #define HID0_par 7
336 #define HID0_parm 0x01000000
337 #define HID0_sten 7
338 #define HID0_stenm 0x01000000
339 #define HID0_doze 8
340 #define HID0_dozem 0x00800000
341 #define HID0_nap 9
342 #define HID0_napm 0x00400000
343 #define HID0_sleep 10
344 #define HID0_sleepm 0x00200000
345 #define HID0_dpm 11
346 #define HID0_dpmm 0x00100000
347 #define HID0_riseg 12
348 #define HID0_risegm 0x00080000
349 #define HID0_eiec 13
350 #define HID0_eiecm 0x00040000
351 #define HID0_mum 14
352 #define HID0_mumm 0x00020000
353 #define HID0_nhr 15
354 #define HID0_nhrm 0x00010000
355 #define HID0_ice 16
356 #define HID0_icem 0x00008000
357 #define HID0_dce 17
358 #define HID0_dcem 0x00004000
359 #define HID0_ilock 18
360 #define HID0_ilockm 0x00002000
361 #define HID0_dlock 19
362 #define HID0_dlockm 0x00001000
363 #define HID0_icfi 20
364 #define HID0_icfim 0x00000800
365 #define HID0_dcfi 21
366 #define HID0_dcfim 0x00000400
367 #define HID0_spd 22
368 #define HID0_spdm 0x00000200
369 #define HID0_sge 24
370 #define HID0_sgem 0x00000080
371 #define HID0_dcfa 25
372 #define HID0_dcfam 0x00000040
373 #define HID0_btic 26
374 #define HID0_bticm 0x00000020
375 #define HID0_lrstk 27
376 #define HID0_lrstkm 0x00000010
377 #define HID0_abe 28
378 #define HID0_abem 0x00000008
379 #define HID0_fold 28
380 #define HID0_foldm 0x00000008
381 #define HID0_bht 29
382 #define HID0_bhtm 0x00000004
383 #define HID0_nopdst 30
384 #define HID0_nopdstm 0x00000002
385 #define HID0_nopti 31
386 #define HID0_noptim 0x00000001
387
388 #endif
389

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