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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: machine_iq80321.c,v 1.26 2007/06/15 18:08:10 debug Exp $ |
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* |
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* COMMENT: Intel IQ80321 (ARM) |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "bus_pci.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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MACHINE_SETUP(iq80321) |
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{ |
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char tmpstr[300]; |
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struct pci_data *pci; |
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|
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/* |
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* Intel IQ80321. See http://sources.redhat.com/ecos/ |
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* docs-latest/redboot/iq80321.html |
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* for more details about the memory map. |
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*/ |
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|
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machine->machine_name = "Intel IQ80321"; |
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|
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cpu->cd.arm.coproc[6] = arm_coproc_i80321_6; |
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|
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snprintf(tmpstr, sizeof(tmpstr), "i80321 irq=%s.cpu[%i].irq " |
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"addr=0xffffe000", machine->path, machine->bootstrap_cpu); |
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pci = device_add(machine, tmpstr); |
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|
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snprintf(tmpstr, sizeof(tmpstr), "ns16550 irq=%s.cpu[%i].irq." |
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"i80321.%i addr=0xfe800000 name2='serial console'", |
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machine->path, machine->bootstrap_cpu, 28); |
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device_add(machine, tmpstr); |
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|
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/* 0xa0000000 = physical ram, 0xc0000000 = uncached */ |
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dev_ram_init(machine, 0xa0000000, 0x20000000, DEV_RAM_MIRROR, 0x0); |
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dev_ram_init(machine, 0xc0000000, 0x20000000, DEV_RAM_MIRROR, 0x0); |
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|
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/* 0xe0000000 and 0xff000000 = cache flush regions */ |
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dev_ram_init(machine, 0xe0000000, 0x100000, DEV_RAM_RAM, 0x0); |
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dev_ram_init(machine, 0xff000000, 0x100000, DEV_RAM_RAM, 0x0); |
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|
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device_add(machine, "iq80321_7seg addr=0xfe840000"); |
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|
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/* TODO: "Intel i82546EB 1000BASE-T Ethernet" */ |
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|
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/* |
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* "Intel 31244 Serial ATA Controller", must be at device 6 according |
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* to NetBSD's iq80321/iq80321_pci.c:iq80321_pci_intr_map(). |
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*/ |
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bus_pci_add(machine, pci, machine->memory, 0, 6, 0, "i31244"); |
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|
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if (!machine->prom_emulation) |
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return; |
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|
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arm_setup_initial_translation_table(cpu, 0x4000); |
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arm_translation_table_set_l1(cpu, 0xa0000000, 0xa0000000); |
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arm_translation_table_set_l1(cpu, 0xc0000000, 0xa0000000); |
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arm_translation_table_set_l1(cpu, 0xe0000000, 0xe0000000); |
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arm_translation_table_set_l1(cpu, 0xf0000000, 0xf0000000); |
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} |
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|
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|
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MACHINE_DEFAULT_CPU(iq80321) |
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{ |
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machine->cpu_name = strdup("80321_600_2"); |
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} |
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|
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|
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MACHINE_REGISTER(iq80321) |
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{ |
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MR_DEFAULT(iq80321, "Intel IQ80321", ARCH_ARM, MACHINE_IQ80321); |
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|
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machine_entry_add_alias(me, "iq80321"); |
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} |
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|