| 1 |
/* GXemul: $Id: mvme_pcctworeg.h,v 1.1 2007/05/15 12:35:14 debug Exp $ */ |
| 2 |
/* $OpenBSD: pcctworeg.h,v 1.8 2006/04/27 20:19:28 miod Exp $ */ |
| 3 |
|
| 4 |
#ifndef MVME_PCCTWOREG_H |
| 5 |
#define MVME_PCCTWOREG_H |
| 6 |
|
| 7 |
/* |
| 8 |
* Memory map for PCC2 chip found in MVME1x7 boards. |
| 9 |
* |
| 10 |
* PCCchip2 control and status register can be accessed as bytes (8 bits), |
| 11 |
* two-bytes (16 bits), or four-bytes (32 bits). |
| 12 |
*/ |
| 13 |
|
| 14 |
#define PCC2_BASE 0xfff42000 |
| 15 |
#define PCC2_SIZE 0x0040 |
| 16 |
|
| 17 |
#define PCCTWO_CHIPID 0x0000 |
| 18 |
#define PCCTWO_CHIPREV 0x0001 |
| 19 |
#define PCCTWO_GENCTL 0x0002 |
| 20 |
#define PCCTWO_VECBASE 0x0003 |
| 21 |
#define PCCTWO_T1CMP 0x0004 |
| 22 |
#define PCCTWO_T1COUNT 0x0008 |
| 23 |
#define PCCTWO_T2CMP 0x000c |
| 24 |
#define PCCTWO_T2COUNT 0x0010 |
| 25 |
#define PCCTWO_PSCALECNT 0x0014 |
| 26 |
#define PCCTWO_PSCALEADJ 0x0015 |
| 27 |
#define PCCTWO_T2CTL 0x0016 |
| 28 |
#define PCCTWO_T1CTL 0x0017 |
| 29 |
#define PCCTWO_GPIO_ICR 0x0018 |
| 30 |
#define PCCTWO_GPIO_PCR 0x0019 |
| 31 |
#define PCCTWO_T2ICR 0x001a |
| 32 |
#define PCCTWO_T1ICR 0x001b |
| 33 |
#define PCCTWO_SCCERR 0x001c |
| 34 |
#define PCCTWO_SCCICR 0x001d |
| 35 |
#define PCCTWO_SCCTX 0x001e |
| 36 |
#define PCCTWO_SCCRX 0x001f |
| 37 |
#define PCCTWO_SCCMOIACK 0x0023 |
| 38 |
#define PCCTWO_SCCTXIACK 0x0025 |
| 39 |
#define PCCTWO_SCCRXIACK 0x0027 |
| 40 |
#define PCCTWO_IEERR 0x0028 |
| 41 |
#define PCCTWO_IEICR 0x002a |
| 42 |
#define PCCTWO_IEBERR 0x002b |
| 43 |
#define PCCTWO_SCSIERR 0x002c |
| 44 |
#define PCCTWO_SCSIICR 0x002f |
| 45 |
#define PCCTWO_PRTICR 0x0030 |
| 46 |
#define PCCTWO_PTRFICR 0x0031 |
| 47 |
#define PCCTWO_PTRSICR 0x0032 |
| 48 |
#define PCCTWO_PTRPICR 0x0033 |
| 49 |
#define PCCTWO_PRTBICR 0x0034 |
| 50 |
#define PCCTWO_PRTSTATUS 0x0036 |
| 51 |
#define PCCTWO_PRTCTL 0x0037 |
| 52 |
#define PCCTWO_SPEED 0x0038 |
| 53 |
#define PCCTWO_PRTDATA 0x003a |
| 54 |
/* The following registers are not valid on MVME197 */ |
| 55 |
#define PCCTWO_IPL 0x003e |
| 56 |
#define PCCTWO_MASK 0x003f |
| 57 |
|
| 58 |
#define PCC2_ID 0x20 /* value at CHIPID */ |
| 59 |
|
| 60 |
/* General Control Register */ |
| 61 |
#define PCC2_DR0 0x80 |
| 62 |
#define PCC2_C040 0x04 |
| 63 |
#define PCC2_MIEN 0x02 |
| 64 |
#define PCC2_FAST 0x01 |
| 65 |
|
| 66 |
/* Top 4 bits of the PCC2 VBR. Will be the top 4 bits of the vector */ |
| 67 |
#define PCC2_VECT 0x50 |
| 68 |
|
| 69 |
/* Bottom 4 bits of the vector returned during IACK cycle */ |
| 70 |
#define PCC2V_PPBUSY 0x00 /* lowest */ |
| 71 |
#define PCC2V_PPPE 0x01 |
| 72 |
#define PCC2V_PPSELECT 0x02 |
| 73 |
#define PCC2V_PPFAULT 0x03 |
| 74 |
#define PCC2V_PPACK 0x04 |
| 75 |
#define PCC2V_SCSI 0x05 |
| 76 |
#define PCC2V_IEFAIL 0x06 |
| 77 |
#define PCC2V_IE 0x07 |
| 78 |
#define PCC2V_TIMER2 0x08 |
| 79 |
#define PCC2V_TIMER1 0x09 |
| 80 |
#define PCC2V_GPIO 0x0a |
| 81 |
#define PCC2V_SCC_RXE 0x0c |
| 82 |
#define PCC2V_SCC_M (PCC2V_SCC_RXE + 1) |
| 83 |
#define PCC2V_SCC_TX (PCC2V_SCC_M + 1) |
| 84 |
#define PCC2V_SCC_RX (PCC2V_SCC_TX + 1) |
| 85 |
|
| 86 |
#if 0 |
| 87 |
/* |
| 88 |
* Vaddrs for interrupt mask and pri registers |
| 89 |
*/ |
| 90 |
extern u_int8_t *volatile pcc2intr_mask; |
| 91 |
extern u_int8_t *volatile pcc2intr_ipl; |
| 92 |
#endif |
| 93 |
|
| 94 |
/* |
| 95 |
* We lock off our interrupt vector at 0x50. |
| 96 |
*/ |
| 97 |
#define PCC2_VECBASE 0x50 |
| 98 |
#define PCC2_NVEC 0x10 |
| 99 |
|
| 100 |
#define PCC2_TCTL_CEN 0x01 |
| 101 |
#define PCC2_TCTL_COC 0x02 |
| 102 |
#define PCC2_TCTL_COVF 0x04 |
| 103 |
#define PCC2_TCTL_OVF 0xf0 |
| 104 |
|
| 105 |
#define PCC2_GPIO_PLTY 0x80 |
| 106 |
#define PCC2_GPIO_EL 0x40 |
| 107 |
|
| 108 |
#define PCC2_GPIOCR_OE 0x2 |
| 109 |
#define PCC2_GPIOCR_O 0x1 |
| 110 |
|
| 111 |
#define PCC2_SCC_AVEC 0x08 |
| 112 |
|
| 113 |
#define PCC2_SC_INHIBIT (0 << 6) |
| 114 |
#define PCC2_SC_SNOOP (1 << 6) |
| 115 |
#define PCC2_SC_INVAL (2 << 6) |
| 116 |
#define PCC2_SC_RESV (3 << 6) |
| 117 |
|
| 118 |
#define pcc2_timer_us2lim(us) (us) /* timer increments in "us" */ |
| 119 |
|
| 120 |
#define PCC2_IRQ_IPL 0x07 |
| 121 |
#define PCC2_IRQ_ICLR 0x08 |
| 122 |
#define PCC2_IRQ_IEN 0x10 |
| 123 |
#define PCC2_IRQ_INT 0x20 |
| 124 |
|
| 125 |
/* Tick Timer Interrupt Control Register */ |
| 126 |
#define PCC2_TTIRQ_INT 0x20 |
| 127 |
#define PCC2_TTIRQ_IEN 0x10 |
| 128 |
#define PCC2_TTIRQ_ICLR 0x08 |
| 129 |
#define PCC2_TTIRQ_IL 0x07 /* mask for IL2-IL0 */ |
| 130 |
|
| 131 |
#define PCC2_IEERR_SCLR 0x01 |
| 132 |
|
| 133 |
#define PCC2_GENCTL_FAST 0x01 |
| 134 |
#define PCC2_GENCTL_IEN 0x02 |
| 135 |
#define PCC2_GENCTL_C040 0x03 |
| 136 |
|
| 137 |
#endif /* MVME_PCCTWOREG_H */ |
Parent Directory
| 
Revision Log