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/* GXemul: $Id: gtreg.h,v 1.3 2006/09/23 03:52:10 debug Exp $ */ |
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/* $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $ */ |
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|
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/* |
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* This is basically malta/dev/gtreg.h from NetBSD, with additional |
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* defines that Linux uses. Symbol names are practically the same in |
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* NetBSD and Linux, which simplifies things. |
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* |
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* Also parts from cobalt/dev/gtreg.h from NetBSD. |
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* |
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* TODO: Find a better gtreg.h. |
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*/ |
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|
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#ifndef GTREG_H |
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#define GTREG_H |
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|
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#define GT_REGVAL(x) *((volatile u_int32_t *) \ |
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(MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x)))) |
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|
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/* CPU Configuration Register Map */ |
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#define GT_CPU_INT 0x000 |
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#define GT_MULTIGT 0x120 |
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|
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/* CPU Address Decode Register Map */ |
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#define GT_PCI0IOLD_OFS 0x048 |
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#define GT_PCI0IOHD_OFS 0x050 |
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#define GT_PCI0M0LD_OFS 0x058 |
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#define GT_PCI0M0HD_OFS 0x060 |
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#define GT_PCI0M1LD_OFS 0x080 |
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#define GT_PCI0M1HD_OFS 0x088 |
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#define GT_PCI0IOREMAP_OFS 0x0f0 |
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#define GT_PCI0M0REMAP_OFS 0x0f8 |
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#define GT_PCI0M1REMAP_OFS 0x100 |
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|
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#define GT_N_DECODE_REGS (0x108 / 8) |
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|
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/* CPU Error Report Register Map */ |
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|
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/* CPU Sync Barrier Register Map */ |
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|
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/* SDRAM and Device Address Decode Register Map */ |
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|
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/* SDRAM Configuration Register Map */ |
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|
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/* SDRAM Parameters Register Map */ |
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|
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/* ECC Register Map */ |
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|
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/* Device Parameters Register Map */ |
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|
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/* DMA Record Register Map */ |
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|
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/* DMA Arbiter Register Map */ |
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|
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/* Timer/Counter Register Map */ |
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#define GT_TIMER_COUNTER0 0x850 |
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#define GT_TIMER_COUNTER1 0x854 |
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#define GT_TIMER_COUNTER2 0x858 |
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#define GT_TIMER_COUNTER3 0x85c |
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|
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#define GT_TIMER_CTRL 0x864 |
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#define ENTC0 0x01 |
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#define TCSEL0 0x02 |
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#define ENTC1 0x04 |
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#define TCSEL1 0x08 |
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#define ENTC2 0x10 |
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#define TCSEL2 0x20 |
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#define ENTC3 0x40 |
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#define TCSEL3 0x80 |
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|
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/* PCI Internal Register Map */ |
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#define GT_PCI0_CMD_OFS 0xc00 |
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#define GT_PCI0_CFG_ADDR 0xcf8 |
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#define GT_PCI0_CFG_DATA 0xcfc |
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#define GT_PCI0_INTR_ACK 0xc34 |
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|
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/* Interrupts Register Map */ |
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#define GT_INTR_CAUSE 0xc18 |
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#define GTIC_INTSUM 0x00000001 |
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#define GTIC_MEMOUT 0x00000002 |
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#define GTIC_DMAOUT 0x00000004 |
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#define GTIC_CPUOUT 0x00000008 |
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#define GTIC_DMA0COMP 0x00000010 |
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#define GTIC_DMA1COMP 0x00000020 |
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#define GTIC_DMA2COMP 0x00000040 |
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#define GTIC_DMA3COMP 0x00000080 |
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#define GTIC_T0EXP 0x00000100 |
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#define GTIC_T1EXP 0x00000200 |
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#define GTIC_T2EXP 0x00000400 |
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#define GTIC_T3EXP 0x00000800 |
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#define GTIC_MASRDERR0 0x00001000 |
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#define GTIC_SLVWRERR0 0x00002000 |
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#define GTIC_MASWRERR0 0x00004000 |
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#define GTIC_SLVRDERR0 0x00008000 |
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#define GTIC_ADDRERR0 0x00010000 |
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#define GTIC_MEMERR 0x00020000 |
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#define GTIC_MASABORT0 0x00040000 |
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#define GTIC_TARABORT0 0x00080000 |
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#define GTIC_RETRYCNT0 0x00100000 |
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#define GTIC_PMCINT_0 0x00200000 |
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#define GTIC_CPUINT 0x0c300000 |
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#define GTIC_PCINT 0xc3000000 |
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#define GTIC_CPUINTSUM 0x40000000 |
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#define GTIC_PCIINTSUM 0x80000000 |
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|
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/* PCI Configuration Register Map */ |
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//#define GT_PCICONFIGBASE 0 |
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//#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00) |
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//#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04) |
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//#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08) |
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//#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c) |
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//#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10) |
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//#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14) |
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//#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18) |
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//#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30) |
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//#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c) |
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|
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/* PCI Configuration, Function 1, Register Map */ |
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|
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/* I2O Support Register Map */ |
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|
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#endif /* !GTREG_H */ |
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