src/include/cpu_alpha.h

#ifndef CPU_ALPHA_H
#define CPU_ALPHA_H

/*
 *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_alpha.h,v 1.48 2007/06/07 15:36:24 debug Exp $
 */

#include "misc.h"

#include "alpha_cpu.h"

struct timer;


/*  ALPHA CPU types:  */
struct alpha_cpu_type_def { 
        char            *name;
        uint64_t        pcs_type;       /*  See alpha_rpb.h  */
        int             features;
        int             implver;
        int             icache_shift;
        int             ilinesize;
        int             iway;
        int             dcache_shift;
        int             dlinesize;
        int             dway;
        int             l2cache_shift;
        int             l2linesize;
        int             l2way;
};

/*  TODO: More features  */
#define ALPHA_FEATURE_BWX               1

#define ALPHA_CPU_TYPE_DEFS     {                                       \
        { "21064",      0x000000002ULL, 0, 0, 16,5,2, 16,5,2,  0,0,0 }, \
        { "21066",      0x200000004ULL, 0, 0, 16,5,2, 16,5,2,  0,0,0 }, \
        { "21164",      0x000000005ULL, 0, 1, 16,5,2, 16,5,2,  0,0,0 }, \
        { "21164A-2",   0x000000007ULL, 0, 1, 16,5,2, 16,5,2,  0,0,0 }, \
        { "21164PC",    0x000000009ULL, 0, 1, 16,5,2, 16,5,2,  0,0,0 }, \
        { "21264",      0x00000000dULL, 0, 2, 16,5,2, 16,5,2,  0,0,0 }, \
        { "21364",      0x000000000ULL, 0, 3, 16,5,2, 16,5,2,  0,0,0 }, \
        { NULL,         0x000000000ULL, 0, 0,  0,0,0,  0,0,0,  0,0,0 }  }


struct cpu_family;

/*  ALPHA_KENTRY_INT .. ALPHA_KENTRY_SYS  */
#define N_ALPHA_KENTRY          6

#define ALPHA_V0                0
#define ALPHA_A0                16
#define ALPHA_A1                17
#define ALPHA_A2                18
#define ALPHA_A3                19
#define ALPHA_A4                20
#define ALPHA_A5                21
#define ALPHA_RA                26
#define ALPHA_T12               27
#define ALPHA_SP                30
#define ALPHA_ZERO              31
#define N_ALPHA_REGS            32

#define ALPHA_REG_NAMES         {                               \
        "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",         \
        "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",         \
        "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",         \
        "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero"     }


/*  Dyntrans definitions:  */

#define ALPHA_N_IC_ARGS                 3
#define ALPHA_INSTR_ALIGNMENT_SHIFT     2
#define ALPHA_IC_ENTRIES_SHIFT          11
#define ALPHA_IC_ENTRIES_PER_PAGE       (1 << ALPHA_IC_ENTRIES_SHIFT)
#define ALPHA_PC_TO_IC_ENTRY(a)         (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
                                        & (ALPHA_IC_ENTRIES_PER_PAGE-1))
#define ALPHA_ADDR_TO_PAGENR(a)         ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
                                        + ALPHA_INSTR_ALIGNMENT_SHIFT))

#define ALPHA_MAX_VPH_TLB_ENTRIES       128

#define ALPHA_L2N               17
#define ALPHA_L3N               17

DYNTRANS_MISC_DECLARATIONS(alpha,ALPHA,uint64_t)
DYNTRANS_MISC64_DECLARATIONS(alpha,ALPHA,uint8_t)


#define ALPHA_PAGESHIFT         13


struct alpha_cpu {
        struct alpha_cpu_type_def       cpu_type;


        /*
         *  General Purpose Registers:
         */

        uint64_t                r[N_ALPHA_REGS];        /*  Integer  */
        uint64_t                f[N_ALPHA_REGS];        /*  Floating Point  */

        uint64_t                fpcr;                   /*  FP Control Reg.  */

        /*  Misc.:  */
        uint64_t                pcc;                    /*  Cycle Counter  */
        uint64_t                ipl;
        uint64_t                load_linked_addr;
        int                     ll_flag;

        int                     irq_asserted;

        /*  OSF1 PALcode specific:  */
        uint64_t                vptptr;         /*  Virtual Page Table Ptr  */
        uint64_t                sysvalue;
        uint64_t                kgp;            /*  Kernel GP  */
        uint64_t                kentry[N_ALPHA_KENTRY];
        uint64_t                ctx;            /*  Ptr to current PCB (?)  */
        struct alpha_pcb        pcb;            /*  Process Control Block  */


        /*
         *  Instruction translation cache and Virtual->Physical->Host
         *  address translation:
         */
        DYNTRANS_ITC(alpha)
        VPH_TLBS(alpha,ALPHA)
        VPH64(alpha,ALPHA)
};


/*  cpu_alpha.c:  */
void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
        unsigned char *host_page, int writeflag, uint64_t paddr_page);
void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
void alpha_init_64bit_dummy_tables(struct cpu *cpu);
void alpha_timer_sample_tick(struct timer *, void *);
int alpha_run_instr(struct cpu *cpu);
int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
        unsigned char *data, size_t len, int writeflag, int cache_flags);
int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem,
        uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
        int cache_flags);
int alpha_cpu_family_init(struct cpu_family *);

/*  cpu_alpha_palcode.c:  */
void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
void alpha_palcode(struct cpu *cpu, uint32_t palcode);

/*  memory_alpha.c:  */
int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr,
        uint64_t *return_addr, int flags);


#endif  /*  CPU_ALPHA_H  */
1	#ifndef CPU_ALPHA_H
2	#define CPU_ALPHA_H
3
4	/*
5	* Copyright (C) 2005-2007 Anders Gavare. All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions are met:
9	*
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* 3. The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*
31	* $Id: cpu_alpha.h,v 1.48 2007/06/07 15:36:24 debug Exp $
32	*/
33
34	#include "misc.h"
35
36	#include "alpha_cpu.h"
37
38	struct timer;
39
40
41	/* ALPHA CPU types: */
42	struct alpha_cpu_type_def {
43	char *name;
44	uint64_t pcs_type; /* See alpha_rpb.h */
45	int features;
46	int implver;
47	int icache_shift;
48	int ilinesize;
49	int iway;
50	int dcache_shift;
51	int dlinesize;
52	int dway;
53	int l2cache_shift;
54	int l2linesize;
55	int l2way;
56	};
57
58	/* TODO: More features */
59	#define ALPHA_FEATURE_BWX 1
60
61	#define ALPHA_CPU_TYPE_DEFS { \
62	{ "21064", 0x000000002ULL, 0, 0, 16,5,2, 16,5,2, 0,0,0 }, \
63	{ "21066", 0x200000004ULL, 0, 0, 16,5,2, 16,5,2, 0,0,0 }, \
64	{ "21164", 0x000000005ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \
65	{ "21164A-2", 0x000000007ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \
66	{ "21164PC", 0x000000009ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \
67	{ "21264", 0x00000000dULL, 0, 2, 16,5,2, 16,5,2, 0,0,0 }, \
68	{ "21364", 0x000000000ULL, 0, 3, 16,5,2, 16,5,2, 0,0,0 }, \
69	{ NULL, 0x000000000ULL, 0, 0, 0,0,0, 0,0,0, 0,0,0 } }
70
71
72	struct cpu_family;
73
74	/* ALPHA_KENTRY_INT .. ALPHA_KENTRY_SYS */
75	#define N_ALPHA_KENTRY 6
76
77	#define ALPHA_V0 0
78	#define ALPHA_A0 16
79	#define ALPHA_A1 17
80	#define ALPHA_A2 18
81	#define ALPHA_A3 19
82	#define ALPHA_A4 20
83	#define ALPHA_A5 21
84	#define ALPHA_RA 26
85	#define ALPHA_T12 27
86	#define ALPHA_SP 30
87	#define ALPHA_ZERO 31
88	#define N_ALPHA_REGS 32
89
90	#define ALPHA_REG_NAMES { \
91	"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \
92	"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \
93	"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \
94	"t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" }
95
96
97	/* Dyntrans definitions: */
98
99	#define ALPHA_N_IC_ARGS 3
100	#define ALPHA_INSTR_ALIGNMENT_SHIFT 2
101	#define ALPHA_IC_ENTRIES_SHIFT 11
102	#define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT)
103	#define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \
104	& (ALPHA_IC_ENTRIES_PER_PAGE-1))
105	#define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \
106	+ ALPHA_INSTR_ALIGNMENT_SHIFT))
107
108	#define ALPHA_MAX_VPH_TLB_ENTRIES 128
109
110	#define ALPHA_L2N 17
111	#define ALPHA_L3N 17
112
113	DYNTRANS_MISC_DECLARATIONS(alpha,ALPHA,uint64_t)
114	DYNTRANS_MISC64_DECLARATIONS(alpha,ALPHA,uint8_t)
115
116
117	#define ALPHA_PAGESHIFT 13
118
119
120	struct alpha_cpu {
121	struct alpha_cpu_type_def cpu_type;
122
123
124	/*
125	* General Purpose Registers:
126	*/
127
128	uint64_t r[N_ALPHA_REGS]; /* Integer */
129	uint64_t f[N_ALPHA_REGS]; /* Floating Point */
130
131	uint64_t fpcr; /* FP Control Reg. */
132
133	/* Misc.: */
134	uint64_t pcc; /* Cycle Counter */
135	uint64_t ipl;
136	uint64_t load_linked_addr;
137	int ll_flag;
138
139	int irq_asserted;
140
141	/* OSF1 PALcode specific: */
142	uint64_t vptptr; /* Virtual Page Table Ptr */
143	uint64_t sysvalue;
144	uint64_t kgp; /* Kernel GP */
145	uint64_t kentry[N_ALPHA_KENTRY];
146	uint64_t ctx; /* Ptr to current PCB (?) */
147	struct alpha_pcb pcb; /* Process Control Block */
148
149
150	/*
151	* Instruction translation cache and Virtual->Physical->Host
152	* address translation:
153	*/
154	DYNTRANS_ITC(alpha)
155	VPH_TLBS(alpha,ALPHA)
156	VPH64(alpha,ALPHA)
157	};
158
159
160	/* cpu_alpha.c: */
161	void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
162	unsigned char *host_page, int writeflag, uint64_t paddr_page);
163	void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
164	void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
165	void alpha_init_64bit_dummy_tables(struct cpu *cpu);
166	void alpha_timer_sample_tick(struct timer , void );
167	int alpha_run_instr(struct cpu *cpu);
168	int alpha_memory_rw(struct cpu cpu, struct memory mem, uint64_t vaddr,
169	unsigned char *data, size_t len, int writeflag, int cache_flags);
170	int alpha_userland_memory_rw(struct cpu cpu, struct memory mem,
171	uint64_t vaddr, unsigned char *data, size_t len, int writeflag,
172	int cache_flags);
173	int alpha_cpu_family_init(struct cpu_family *);
174
175	/* cpu_alpha_palcode.c: */
176	void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen);
177	void alpha_palcode(struct cpu *cpu, uint32_t palcode);
178
179	/* memory_alpha.c: */
180	int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr,
181	uint64_t *return_addr, int flags);
182
183
184	#endif /* CPU_ALPHA_H */