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#ifndef CPU_H |
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#define CPU_H |
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|
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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu.h,v 1.128 2007/06/14 04:53:14 debug Exp $ |
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* |
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* CPU-related definitions. |
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*/ |
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|
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|
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#include <sys/types.h> |
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#include <inttypes.h> |
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#include <sys/time.h> |
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|
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/* This is needed for undefining 'mips', 'ppc' etc. on weird systems: */ |
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#include "../../config.h" |
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|
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#include "timer.h" |
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|
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|
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/* |
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* Dyntrans misc declarations, used throughout the dyntrans code. |
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* |
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* Note that there is space for all instruction calls within a page, |
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* and then 2 more. The first one of these "extra" instruction slots is |
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* the end-of-page slot. It transfers control to the first instruction |
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* slot on the next (virtual) page. |
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* |
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* The second of these extra instruction slots is an additional |
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* end-of-page slot for delay-slot architectures. On e.g. MIPS, a branch |
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* instruction can "nullify" (skip) the delay-slot. If the end-of-page |
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* slot is skipped, then we end up one step after that. That's where the |
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* end_of_page2 slot is. :) |
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* |
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* next_ofs points to the next page in a chain of possible pages. |
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* (several pages can be in the same chain, but only one matches the |
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* specific physaddr.) |
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* |
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* translations is a tiny bitmap indicating which parts of the page have |
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* actual translations. Bit 0 corresponds to the lowest 1/32th of the page, |
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* bit 1 to the second-lowest 1/32th, and so on. This speeds up page |
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* invalidations, since only part of the page need to be reset. |
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*/ |
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#define DYNTRANS_MISC_DECLARATIONS(arch,ARCH,addrtype) struct \ |
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arch ## _instr_call { \ |
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void (*f)(struct cpu *, struct arch ## _instr_call *); \ |
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size_t arg[ARCH ## _N_IC_ARGS]; \ |
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}; \ |
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\ |
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/* Translation cache struct for each physical page: */ \ |
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struct arch ## _tc_physpage { \ |
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struct arch ## _instr_call ics[ARCH ## _IC_ENTRIES_PER_PAGE+2];\ |
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uint32_t next_ofs; /* (0 for end of chain) */ \ |
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uint32_t translations; \ |
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addrtype physaddr; \ |
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}; \ |
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\ |
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struct arch ## _vpg_tlb_entry { \ |
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uint8_t valid; \ |
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uint8_t writeflag; \ |
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addrtype vaddr_page; \ |
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addrtype paddr_page; \ |
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unsigned char *host_page; \ |
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}; |
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|
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#define DYNTRANS_MISC64_DECLARATIONS(arch,ARCH,tlbindextype) \ |
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struct arch ## _l3_64_table { \ |
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unsigned char *host_load[1 << ARCH ## _L3N]; \ |
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unsigned char *host_store[1 << ARCH ## _L3N]; \ |
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uint64_t phys_addr[1 << ARCH ## _L3N]; \ |
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tlbindextype vaddr_to_tlbindex[1 << ARCH ## _L3N]; \ |
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struct arch ## _tc_physpage *phys_page[1 << ARCH ## _L3N]; \ |
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struct arch ## _l3_64_table *next; \ |
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int refcount; \ |
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}; \ |
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struct arch ## _l2_64_table { \ |
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struct arch ## _l3_64_table *l3[1 << ARCH ## _L2N]; \ |
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struct arch ## _l2_64_table *next; \ |
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int refcount; \ |
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}; |
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|
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/* |
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* Dyntrans "Instruction Translation Cache": |
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* |
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* cur_physpage is a pointer to the current physpage. (It _HAPPENS_ to |
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* be the same as cur_ic_page, because all the instrcalls should be placed |
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* first in the physpage struct!) |
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* |
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* cur_ic_page is a pointer to an array of xxx_IC_ENTRIES_PER_PAGE |
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* instruction call entries. |
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* |
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* next_ic points to the next such instruction call to be executed. |
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* |
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* combination_check, when set to non-NULL, is executed automatically after |
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* an instruction has been translated. (It check for combinations of |
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* instructions; low_addr is the offset of the translated instruction in the |
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* current page, NOT shifted right.) |
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*/ |
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#define DYNTRANS_ITC(arch) struct arch ## _tc_physpage *cur_physpage; \ |
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struct arch ## _instr_call *cur_ic_page; \ |
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struct arch ## _instr_call *next_ic; \ |
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struct arch ## _tc_physpage *physpage_template;\ |
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void (*combination_check)(struct cpu *, \ |
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struct arch ## _instr_call *, int low_addr); |
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|
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/* |
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* Virtual -> physical -> host address translation TLB entries: |
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* ------------------------------------------------------------ |
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* |
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* Regardless of whether 32-bit or 64-bit address translation is used, the |
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* same TLB entry structure is used. |
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*/ |
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#define VPH_TLBS(arch,ARCH) \ |
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struct arch ## _vpg_tlb_entry \ |
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vph_tlb_entry[ARCH ## _MAX_VPH_TLB_ENTRIES]; |
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|
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/* |
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* 32-bit dyntrans emulated Virtual -> physical -> host address translation: |
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* ------------------------------------------------------------------------- |
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* |
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* This stuff assumes that 4 KB pages are used. 20 bits to select a page |
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* means just 1 M entries needed. This is small enough that a couple of |
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* full-size tables can fit in virtual memory on modern hosts (both 32-bit |
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* and 64-bit hosts). :-) |
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* |
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* Usage: e.g. VPH32(arm,ARM) |
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* or VPH32(sparc,SPARC) |
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* |
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* The vph_tlb_entry entries are cpu dependent tlb entries. |
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* |
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* The host_load and host_store entries point to host pages; the phys_addr |
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* entries are uint32_t (emulated physical addresses). |
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* |
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* phys_page points to translation cache physpages. |
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* |
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* vaddr_to_tlbindex is a virtual address to tlb index hint table. |
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* The values in this array are the tlb index plus 1, so a value of, say, |
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* 3 means tlb index 2. A value of 0 would mean a tlb index of -1, which |
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* is not a valid index. (I.e. no hit.) |
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* |
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* The VPH32EXTENDED variant adds an additional postfix to the array |
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* names. Used so far only for usermode addresses in M88K emulation. |
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*/ |
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#define N_VPH32_ENTRIES 1048576 |
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#define VPH32(arch,ARCH) \ |
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unsigned char *host_load[N_VPH32_ENTRIES]; \ |
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unsigned char *host_store[N_VPH32_ENTRIES]; \ |
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uint32_t phys_addr[N_VPH32_ENTRIES]; \ |
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struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \ |
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uint8_t vaddr_to_tlbindex[N_VPH32_ENTRIES]; |
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#define VPH32_16BITVPHENTRIES(arch,ARCH) \ |
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unsigned char *host_load[N_VPH32_ENTRIES]; \ |
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unsigned char *host_store[N_VPH32_ENTRIES]; \ |
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uint32_t phys_addr[N_VPH32_ENTRIES]; \ |
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struct arch ## _tc_physpage *phys_page[N_VPH32_ENTRIES]; \ |
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uint16_t vaddr_to_tlbindex[N_VPH32_ENTRIES]; |
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#define VPH32EXTENDED(arch,ARCH,ex) \ |
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unsigned char *host_load_ ## ex[N_VPH32_ENTRIES]; \ |
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unsigned char *host_store_ ## ex[N_VPH32_ENTRIES]; \ |
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uint32_t phys_addr_ ## ex[N_VPH32_ENTRIES]; \ |
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struct arch ## _tc_physpage *phys_page_ ## ex[N_VPH32_ENTRIES];\ |
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uint8_t vaddr_to_tlbindex_ ## ex[N_VPH32_ENTRIES]; |
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|
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|
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/* |
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* 64-bit dyntrans emulated Virtual -> physical -> host address translation: |
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* ------------------------------------------------------------------------- |
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* |
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* Usage: e.g. VPH64(alpha,ALPHA) |
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* or VPH64(sparc,SPARC) |
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* |
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* l1_64 is an array containing poiners to l2 tables. |
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* |
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* l2_64_dummy is a pointer to a "dummy l2 table". Instead of having NULL |
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* pointers in l1_64 for unused slots, a pointer to the dummy table can be |
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* used. |
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*/ |
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#define DYNTRANS_L1N 17 |
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#define VPH64(arch,ARCH) \ |
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struct arch ## _l3_64_table *l3_64_dummy; \ |
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struct arch ## _l3_64_table *next_free_l3; \ |
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struct arch ## _l2_64_table *l2_64_dummy; \ |
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struct arch ## _l2_64_table *next_free_l2; \ |
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struct arch ## _l2_64_table *l1_64[1 << DYNTRANS_L1N]; |
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|
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|
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/* Include all CPUs' header files here: */ |
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#include "cpu_alpha.h" |
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#include "cpu_arm.h" |
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#include "cpu_m88k.h" |
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#include "cpu_mips.h" |
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#include "cpu_ppc.h" |
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#include "cpu_sh.h" |
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#include "cpu_sparc.h" |
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|
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struct cpu; |
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struct emul; |
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struct machine; |
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struct memory; |
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struct settings; |
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|
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|
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/* |
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* cpu_family |
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* ---------- |
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* |
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* This structure consists of various pointers to functions, performing |
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* architecture-specific functions. |
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* |
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* Except for the next and arch fields at the top, all fields in the |
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* cpu_family struct are filled in by ecah CPU family's init function. |
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*/ |
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struct cpu_family { |
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struct cpu_family *next; |
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int arch; |
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|
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/* Familty name, e.g. "MIPS", "Alpha" etc. */ |
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char *name; |
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|
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/* Fill in architecture specific parts of a struct cpu. */ |
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int (*cpu_new)(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, |
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int cpu_id, char *cpu_type_name); |
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|
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/* Initialize various translation tables. */ |
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void (*init_tables)(struct cpu *cpu); |
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|
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/* List available CPU types for this architecture. */ |
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void (*list_available_types)(void); |
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|
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/* Disassemble an instruction. */ |
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int (*disassemble_instr)(struct cpu *cpu, |
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unsigned char *instr, int running, |
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uint64_t dumpaddr); |
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|
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/* Dump CPU registers in readable format. */ |
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void (*register_dump)(struct cpu *cpu, |
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int gprs, int coprocs); |
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|
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/* Dump generic CPU info in readable format. */ |
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void (*dumpinfo)(struct cpu *cpu); |
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|
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/* Dump TLB data for CPU id x. */ |
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void (*tlbdump)(struct machine *m, int x, |
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int rawflag); |
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|
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/* Print architecture-specific function call arguments. |
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(This is called for each function call, if running with -t.) */ |
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void (*functioncall_trace)(struct cpu *, |
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uint64_t f, int n_args); |
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}; |
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|
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|
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/* |
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* More dyntrans stuff: |
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* |
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* The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets |
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* into the cache, for possible translation cache structs for physical pages. |
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*/ |
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|
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/* Meaning of delay_slot: */ |
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#define NOT_DELAYED 0 |
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#define DELAYED 1 |
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#define TO_BE_DELAYED 2 |
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#define EXCEPTION_IN_DELAY_SLOT 8 |
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|
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#define N_SAFE_DYNTRANS_LIMIT_SHIFT 14 |
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#define N_SAFE_DYNTRANS_LIMIT ((1 << (N_SAFE_DYNTRANS_LIMIT_SHIFT - 1)) - 1) |
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|
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#define MAX_DYNTRANS_READAHEAD 1024 |
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|
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#define DEFAULT_DYNTRANS_CACHE_SIZE (48*1048576) |
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#define DYNTRANS_CACHE_MARGIN 200000 |
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|
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#define N_BASE_TABLE_ENTRIES 65536 |
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#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
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|
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#define CPU_SAMPLE_TIMER_HZ TIMER_BASE_FREQUENCY |
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#define N_PADDR_SAMPLES 64 |
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|
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|
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/* |
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* The generic CPU struct: |
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*/ |
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|
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struct cpu { |
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/* Pointer back to the machine this CPU is in: */ |
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struct machine *machine; |
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|
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/* Settings: */ |
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struct settings *settings; |
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|
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/* CPU-specific name, e.g. "R2000", "21164PC", etc. */ |
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char *name; |
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|
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/* Full "path" to the CPU, e.g. "emul[0].machine[0].cpu[0]": */ |
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char *path; |
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|
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/* Nr of instructions executed, etc.: */ |
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int64_t ninstrs; |
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int64_t ninstrs_show; |
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int64_t ninstrs_flush; |
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int64_t ninstrs_since_gettimeofday; |
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struct timeval starttime; |
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|
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/* |
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* Periodic sampling of the physical address corresponding to the |
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* emulated program counter: |
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* |
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* (Used to decide whether or not native code generation is worth |
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* the effort.) |
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*/ |
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struct timer *sampling_timer; |
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uint8_t sampling; /* 1 = turned on */ |
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int16_t sampling_curindex; |
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uint64_t *sampling_paddr; |
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|
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/* EMUL_LITTLE_ENDIAN or EMUL_BIG_ENDIAN. */ |
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uint8_t byte_order; |
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|
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/* 0 for emulated 64-bit CPUs, 1 for 32-bit. */ |
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uint8_t is_32bit; |
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|
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/* 1 while running, 0 when paused/stopped. */ |
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uint8_t running; |
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|
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/* See comment further up. */ |
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uint8_t delay_slot; |
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|
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/* 0-based CPU id, in an emulated SMP system. */ |
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int cpu_id; |
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|
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/* A pointer to the main memory connected to this CPU. */ |
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struct memory *mem; |
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|
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int (*run_instr)(struct cpu *cpu); |
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int (*memory_rw)(struct cpu *cpu, |
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struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, |
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int writeflag, int cache_flags); |
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int (*translate_v2p)(struct cpu *, uint64_t vaddr, |
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uint64_t *return_paddr, int flags); |
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void (*update_translation_table)(struct cpu *, |
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uint64_t vaddr_page, unsigned char *host_page, |
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int writeflag, uint64_t paddr_page); |
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void (*invalidate_translation_caches)(struct cpu *, |
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uint64_t paddr, int flags); |
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void (*invalidate_code_translation)(struct cpu *, |
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uint64_t paddr, int flags); |
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void (*useremul_syscall)(struct cpu *cpu, uint32_t code); |
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int (*instruction_has_delayslot)(struct cpu *cpu, |
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unsigned char *ib); |
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|
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/* The program counter. (For 32-bit modes, not all bits are used.) */ |
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uint64_t pc; |
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|
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/* The current depth of function call tracing. */ |
| 384 |
int trace_tree_depth; |
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|
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/* |
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* If is_halted is true when an interrupt trap occurs, the pointer |
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* to the next instruction to execute will be the instruction |
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* following the halt instruction, not the halt instrucion itself. |
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* |
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* If has_been_idling is true when printing the number of executed |
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* instructions per second, "idling" is printed instead. (The number |
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* of instrs per second when idling is meaningless anyway.) |
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*/ |
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char is_halted; |
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char has_been_idling; |
| 397 |
|
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/* |
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* Dynamic translation: |
| 400 |
* |
| 401 |
* The number of translated instructions is assumed to be 1 per |
| 402 |
* instruction call. For each case where this differs from the |
| 403 |
* truth, n_translated_instrs should be modified. E.g. if 1000 |
| 404 |
* instruction calls are done, and n_translated_instrs is 50, then |
| 405 |
* 1050 emulated instructions were actually executed. |
| 406 |
* |
| 407 |
* Note that it can also be adjusted negatively, that is, the way |
| 408 |
* to "get out" of a dyntrans loop is to set the current instruction |
| 409 |
* call pointer to the "nothing" instruction. This instruction |
| 410 |
* _decreases_ n_translated_instrs by 1. That way, once the dyntrans |
| 411 |
* loop exits, only real instructions will be counted, and not the |
| 412 |
* "nothing" instructions. |
| 413 |
* |
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* The translation cache is a relative large chunk of memory (say, |
| 415 |
* 32 MB) which is used for translations. When it has been used up, |
| 416 |
* everything restarts from scratch. |
| 417 |
* |
| 418 |
* translation_readahead is non-zero when translating instructions |
| 419 |
* ahead of the current (emulated) instruction pointer. |
| 420 |
*/ |
| 421 |
|
| 422 |
/* Non-zero when translating ahead of the current instruction: */ |
| 423 |
int translation_readahead; |
| 424 |
|
| 425 |
/* Instruction translation cache: */ |
| 426 |
int n_translated_instrs; |
| 427 |
unsigned char *translation_cache; |
| 428 |
size_t translation_cache_cur_ofs; |
| 429 |
|
| 430 |
|
| 431 |
/* |
| 432 |
* CPU-family dependent: |
| 433 |
* |
| 434 |
* These contain everything ranging from general purpose registers, |
| 435 |
* control registers, memory management, status words, interrupt |
| 436 |
* specifics, etc. |
| 437 |
*/ |
| 438 |
union { |
| 439 |
struct alpha_cpu alpha; |
| 440 |
struct arm_cpu arm; |
| 441 |
struct m88k_cpu m88k; |
| 442 |
struct mips_cpu mips; |
| 443 |
struct ppc_cpu ppc; |
| 444 |
struct sh_cpu sh; |
| 445 |
struct sparc_cpu sparc; |
| 446 |
} cd; |
| 447 |
}; |
| 448 |
|
| 449 |
|
| 450 |
/* cpu.c: */ |
| 451 |
struct cpu *cpu_new(struct memory *mem, struct machine *machine, |
| 452 |
int cpu_id, char *cpu_type_name); |
| 453 |
void cpu_destroy(struct cpu *cpu); |
| 454 |
|
| 455 |
void cpu_tlbdump(struct machine *m, int x, int rawflag); |
| 456 |
void cpu_register_dump(struct machine *m, struct cpu *cpu, |
| 457 |
int gprs, int coprocs); |
| 458 |
int cpu_disassemble_instr(struct machine *m, struct cpu *cpu, |
| 459 |
unsigned char *instr, int running, uint64_t addr); |
| 460 |
|
| 461 |
void cpu_functioncall_trace(struct cpu *cpu, uint64_t f); |
| 462 |
void cpu_functioncall_trace_return(struct cpu *cpu); |
| 463 |
|
| 464 |
void cpu_create_or_reset_tc(struct cpu *cpu); |
| 465 |
|
| 466 |
void cpu_run_init(struct machine *machine); |
| 467 |
void cpu_run_deinit(struct machine *machine); |
| 468 |
|
| 469 |
void cpu_dumpinfo(struct machine *m, struct cpu *cpu); |
| 470 |
void cpu_list_available_types(void); |
| 471 |
void cpu_show_cycles(struct machine *machine, int forced); |
| 472 |
|
| 473 |
struct cpu_family *cpu_family_ptr_by_number(int arch); |
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void cpu_init(void); |
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#define JUST_MARK_AS_NON_WRITABLE 1 |
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#define INVALIDATE_ALL 2 |
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#define INVALIDATE_PADDR 4 |
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#define INVALIDATE_VADDR 8 |
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#define INVALIDATE_VADDR_UPPER4 16 /* useful for PPC emulation */ |
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/* Note: 64-bit processors running in 32-bit mode use a 32-bit |
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display format, even though the underlying data is 64-bits. */ |
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#define CPU_SETTINGS_ADD_REGISTER64(name, var) \ |
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settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT64, \ |
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cpu->is_32bit? SETTINGS_FORMAT_HEX32 : SETTINGS_FORMAT_HEX64, \ |
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(void *) &(var)); |
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#define CPU_SETTINGS_ADD_REGISTER32(name, var) \ |
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settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT32, \ |
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SETTINGS_FORMAT_HEX32, (void *) &(var)); |
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#define CPU_SETTINGS_ADD_REGISTER16(name, var) \ |
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settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT16, \ |
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SETTINGS_FORMAT_HEX16, (void *) &(var)); |
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#define CPU_SETTINGS_ADD_REGISTER8(name, var) \ |
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settings_add(cpu->settings, name, 1, SETTINGS_TYPE_UINT8, \ |
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SETTINGS_FORMAT_HEX8, (void *) &(var)); |
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#define CPU_FAMILY_INIT(n,s) int n ## _cpu_family_init( \ |
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struct cpu_family *fp) { \ |
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/* Fill in the cpu_family struct with valid data for this arch. */ \ |
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fp->name = s; \ |
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fp->cpu_new = n ## _cpu_new; \ |
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fp->list_available_types = n ## _cpu_list_available_types; \ |
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fp->disassemble_instr = n ## _cpu_disassemble_instr; \ |
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fp->register_dump = n ## _cpu_register_dump; \ |
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fp->dumpinfo = n ## _cpu_dumpinfo; \ |
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fp->functioncall_trace = n ## _cpu_functioncall_trace; \ |
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fp->tlbdump = n ## _cpu_tlbdump; \ |
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fp->init_tables = n ## _cpu_init_tables; \ |
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return 1; \ |
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} |
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#endif /* CPU_H */ |
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