1 |
/* |
2 |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
3 |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
6 |
* |
7 |
* 1. Redistributions of source code must retain the above copyright |
8 |
* notice, this list of conditions and the following disclaimer. |
9 |
* 2. Redistributions in binary form must reproduce the above copyright |
10 |
* notice, this list of conditions and the following disclaimer in the |
11 |
* documentation and/or other materials provided with the distribution. |
12 |
* 3. The name of the author may not be used to endorse or promote products |
13 |
* derived from this software without specific prior written permission. |
14 |
* |
15 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
16 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
17 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
18 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
19 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
20 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
21 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
22 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
23 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
24 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
25 |
* SUCH DAMAGE. |
26 |
* |
27 |
* |
28 |
* $Id: dev_ssc.c,v 1.31 2007/06/15 19:57:34 debug Exp $ |
29 |
* |
30 |
* COMMENT: System Support Chip serial controller |
31 |
* |
32 |
* Serial controller on DECsystem 5400 and 5800. |
33 |
* Known as System Support Chip on VAX 3600 (KA650). |
34 |
* |
35 |
* Described around page 80 in the kn210tm1.pdf. |
36 |
*/ |
37 |
|
38 |
#include <stdio.h> |
39 |
#include <stdlib.h> |
40 |
#include <string.h> |
41 |
|
42 |
#include "console.h" |
43 |
#include "cpu.h" |
44 |
#include "devices.h" |
45 |
#include "machine.h" |
46 |
#include "memory.h" |
47 |
#include "misc.h" |
48 |
|
49 |
|
50 |
#define RX_INT_ENABLE 0x40 |
51 |
#define RX_AVAIL 0x80 |
52 |
#define TX_INT_ENABLE 0x40 |
53 |
#define TX_READY 0x80 |
54 |
|
55 |
#define SSC_TICK_SHIFT 14 |
56 |
|
57 |
/* |
58 |
* _TXRX is for debugging putchar/getchar. The other |
59 |
* one is more general. |
60 |
*/ |
61 |
/* #define SSC_DEBUG_TXRX */ |
62 |
#define SSC_DEBUG |
63 |
|
64 |
struct ssc_data { |
65 |
int console_handle; |
66 |
int use_fb; |
67 |
|
68 |
int rx_ctl; |
69 |
int tx_ctl; |
70 |
|
71 |
struct interrupt irq; |
72 |
}; |
73 |
|
74 |
|
75 |
DEVICE_TICK(ssc) |
76 |
{ |
77 |
struct ssc_data *d = extra; |
78 |
|
79 |
d->tx_ctl |= TX_READY; /* transmitter always ready */ |
80 |
|
81 |
d->rx_ctl &= ~RX_AVAIL; |
82 |
if (console_charavail(d->console_handle)) |
83 |
d->rx_ctl |= RX_AVAIL; |
84 |
|
85 |
/* rx interrupts enabled, and char avail? */ |
86 |
if (d->rx_ctl & RX_INT_ENABLE && d->rx_ctl & RX_AVAIL) { |
87 |
/* TODO: This is for 5800 only! */ |
88 |
unsigned char txvector = 0xf8; |
89 |
cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector, |
90 |
1, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL); |
91 |
INTERRUPT_ASSERT(d->irq); |
92 |
} |
93 |
|
94 |
/* tx interrupts enabled? */ |
95 |
if (d->tx_ctl & TX_INT_ENABLE) { |
96 |
/* TODO: This is for 5800 only! */ |
97 |
unsigned char txvector = 0xfc; |
98 |
cpu->memory_rw(cpu, cpu->mem, 0x40000050, &txvector, |
99 |
1, MEM_WRITE, NO_EXCEPTIONS | PHYSICAL); |
100 |
INTERRUPT_ASSERT(d->irq); |
101 |
} |
102 |
} |
103 |
|
104 |
|
105 |
DEVICE_ACCESS(ssc) |
106 |
{ |
107 |
uint64_t idata = 0, odata = 0; |
108 |
struct ssc_data *d = extra; |
109 |
|
110 |
if (writeflag == MEM_WRITE) |
111 |
idata = memory_readmax64(cpu, data, len); |
112 |
|
113 |
dev_ssc_tick(cpu, extra); |
114 |
|
115 |
switch (relative_addr) { |
116 |
case 0x0080: /* receive status */ |
117 |
if (writeflag==MEM_READ) { |
118 |
odata = d->rx_ctl; |
119 |
#ifdef SSC_DEBUG_TXRX |
120 |
debug("[ ssc: read from 0x%08lx: 0x%02x ]\n", |
121 |
(long)relative_addr, (int)odata); |
122 |
#endif |
123 |
} else { |
124 |
d->rx_ctl = idata; |
125 |
|
126 |
INTERRUPT_DEASSERT(d->irq); |
127 |
|
128 |
#ifdef SSC_DEBUG_TXRX |
129 |
debug("[ ssc: write to 0x%08lx: 0x%02x ]\n", |
130 |
(long)relative_addr, (int)idata); |
131 |
#endif |
132 |
} |
133 |
|
134 |
break; |
135 |
case 0x0084: /* receive data */ |
136 |
if (writeflag==MEM_READ) { |
137 |
#ifdef SSC_DEBUG_TXRX |
138 |
debug("[ ssc: read from 0x%08lx ]\n", |
139 |
(long)relative_addr); |
140 |
#endif |
141 |
if (console_charavail(d->console_handle)) |
142 |
odata = console_readchar(d->console_handle); |
143 |
} else { |
144 |
#ifdef SSC_DEBUG_TXRX |
145 |
debug("[ ssc: write to 0x%08lx: 0x%02x ]\n", |
146 |
(long)relative_addr, (int)idata); |
147 |
#endif |
148 |
} |
149 |
|
150 |
break; |
151 |
case 0x0088: /* transmit status */ |
152 |
if (writeflag==MEM_READ) { |
153 |
odata = d->tx_ctl; |
154 |
#ifdef SSC_DEBUG_TXRX |
155 |
debug("[ ssc: read from 0x%08lx: 0x%04x ]\n", |
156 |
(long)relative_addr, (int)odata); |
157 |
#endif |
158 |
} else { |
159 |
d->tx_ctl = idata; |
160 |
|
161 |
INTERRUPT_DEASSERT(d->irq); |
162 |
|
163 |
#ifdef SSC_DEBUG_TXRX |
164 |
debug("[ ssc: write to 0x%08lx: 0x%02x ]\n", |
165 |
(long)relative_addr, (int)idata); |
166 |
#endif |
167 |
} |
168 |
|
169 |
break; |
170 |
case 0x008c: /* transmit data */ |
171 |
if (writeflag==MEM_READ) { |
172 |
debug("[ ssc: read from 0x%08lx ]\n", |
173 |
(long)relative_addr); |
174 |
} else { |
175 |
/* debug("[ ssc: write to 0x%08lx: 0x%02x ]\n", |
176 |
(long)relative_addr, (int)idata); */ |
177 |
console_putchar(d->console_handle, idata); |
178 |
} |
179 |
|
180 |
break; |
181 |
case 0x0100: |
182 |
if (writeflag==MEM_READ) { |
183 |
odata = 128; |
184 |
#ifdef SSC_DEBUG_TXRX |
185 |
debug("[ ssc: read from 0x%08lx: 0x%08lx ]\n", |
186 |
(long)relative_addr, (long)odata); |
187 |
#endif |
188 |
} else { |
189 |
#ifdef SSC_DEBUG_TXRX |
190 |
debug("[ ssc: write to 0x%08lx: 0x%08x ]\n", |
191 |
(long)relative_addr, idata); |
192 |
#endif |
193 |
} |
194 |
|
195 |
break; |
196 |
case 0x0108: |
197 |
if (writeflag==MEM_READ) { |
198 |
debug("[ ssc: read from 0x%08lx ]\n", |
199 |
(long)relative_addr); |
200 |
} else { |
201 |
#ifdef SSC_DEBUG |
202 |
debug("[ ssc: write to 0x%08lx: 0x%08x ]\n", |
203 |
(long)relative_addr, (int)idata); |
204 |
#endif |
205 |
} |
206 |
|
207 |
break; |
208 |
default: |
209 |
if (writeflag==MEM_READ) { |
210 |
debug("[ ssc: read from 0x%08lx ]\n", |
211 |
(long)relative_addr); |
212 |
} else { |
213 |
debug("[ ssc: write to 0x%08lx: 0x%08x ]\n", |
214 |
(long)relative_addr, (int)idata); |
215 |
} |
216 |
} |
217 |
|
218 |
dev_ssc_tick(cpu, extra); |
219 |
|
220 |
if (writeflag == MEM_READ) |
221 |
memory_writemax64(cpu, data, len, odata); |
222 |
|
223 |
return 1; |
224 |
} |
225 |
|
226 |
|
227 |
void dev_ssc_init(struct machine *machine, struct memory *mem, |
228 |
uint64_t baseaddr, char *irq_path, int use_fb) |
229 |
{ |
230 |
struct ssc_data *d; |
231 |
|
232 |
CHECK_ALLOCATION(d = malloc(sizeof(struct ssc_data))); |
233 |
memset(d, 0, sizeof(struct ssc_data)); |
234 |
|
235 |
d->use_fb = use_fb; |
236 |
d->console_handle = console_start_slave(machine, "SSC", 1); |
237 |
|
238 |
INTERRUPT_CONNECT(irq_path, d->irq); |
239 |
|
240 |
memory_device_register(mem, "ssc", baseaddr, DEV_SSC_LENGTH, |
241 |
dev_ssc_access, d, DM_DEFAULT, NULL); |
242 |
|
243 |
machine_add_tickfunction(machine, dev_ssc_tick, d, SSC_TICK_SHIFT); |
244 |
} |
245 |
|