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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_sii.c,v 1.21 2007/06/15 19:57:34 debug Exp $ |
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* |
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* COMMENT: SII SCSI controller, used in some DECstation systems |
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* |
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* TODO: This is huge and ugly. Fix this. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "devices.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "siireg.h" |
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|
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|
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#define SII_TICK_SHIFT 14 |
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|
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|
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struct sii_data { |
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struct interrupt irq; |
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|
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uint64_t buf_start; |
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uint64_t buf_end; |
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|
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int connected; |
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int connected_to_id; |
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|
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int register_choice; |
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SIIRegs siiregs; |
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uint16_t *regs; |
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}; |
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|
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|
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/* |
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* combine_sii_bits(): |
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* |
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* Combines some bits of CSTAT and DSTAT that are connected. |
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*/ |
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void combine_sii_bits(struct sii_data *d) |
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{ |
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int ci, di; |
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|
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di = ((d->siiregs.dstat & SII_MIS) | |
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(d->siiregs.dstat & SII_IBF) | |
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(d->siiregs.dstat & SII_TBE) | |
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(d->siiregs.dstat & SII_DNE))==0? 0 : SII_DI; |
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|
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ci = ((d->siiregs.cstat & SII_RST) | |
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(d->siiregs.cstat & SII_BER) | |
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(d->siiregs.cstat & SII_OBC) | |
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(d->siiregs.cstat & SII_BUF) | |
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(d->siiregs.cstat & SII_LDN) | |
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(d->siiregs.cstat & SII_SCH))==0? 0 : SII_CI; |
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|
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d->siiregs.cstat &= ~(SII_CI | SII_DI); |
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d->siiregs.dstat &= ~(SII_CI | SII_DI); |
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|
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d->siiregs.cstat |= (ci | di); |
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d->siiregs.dstat |= (ci | di); |
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} |
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|
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|
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DEVICE_TICK(sii) |
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{ |
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struct sii_data *d = extra; |
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|
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/* ? */ |
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d->siiregs.dstat = (d->siiregs.dstat & ~0x7) |
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| ((d->siiregs.dstat + 1) & 0x7); |
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|
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/* SCSI Commands: */ |
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|
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if (d->siiregs.comm & SII_CHRESET) { /* (I,T,D) */ |
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/* debug("[ sii: command TODO: CHRESET ]\n"); */ |
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} |
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|
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if (d->siiregs.comm & SII_DISCON) { /* (I,T,D) */ |
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/* debug("[ sii: command TODO: DISCON ]\n"); */ |
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d->siiregs.cstat &= ~SII_CON; /* Connected */ |
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|
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if (d->connected) { |
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d->siiregs.cstat |= SII_SCH; /* State change */ |
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d->connected = 0; |
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} |
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|
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d->siiregs.cstat &= ~SII_SIP; /* Selection in progress */ |
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d->siiregs.comm &= ~SII_DISCON; |
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} |
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|
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if (d->siiregs.comm & SII_REQDATA) { /* (T) */ |
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/* debug("[ sii: command TODO: REQDATA ]\n"); */ |
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} |
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|
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if (d->siiregs.comm & SII_SELECT) { /* (D) */ |
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/* debug("[ sii: command SELECT ]\n"); */ |
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d->siiregs.comm &= ~SII_SELECT; |
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|
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/* slcsr contains the other target's id */ |
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d->siiregs.cstat |= SII_SIP; /* Selection in progress */ |
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d->connected = 0; |
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d->connected_to_id = 0; |
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|
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/* Is the target available for selection? |
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TODO: make this nicer */ |
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#if 0 |
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if ((d->siiregs.slcsr & 7) == 0) { |
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d->siiregs.cstat |= SII_CON; /* Connected */ |
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d->siiregs.cstat |= SII_SCH; /* State change */ |
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d->siiregs.cstat &= ~SII_SIP; /* Sel. in progress */ |
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|
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d->connected = 1; |
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d->connected_to_id = 0; |
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} |
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#endif |
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} |
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|
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if (d->siiregs.comm & SII_INXFER |
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&& (d->siiregs.comm & 0x70) == (d->siiregs.cstat & 0x70) && |
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(d->siiregs.comm & 0x03) == (d->siiregs.dstat & 0x03) && |
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!(d->siiregs.cstat & SII_SIP)) { /* (I,T) */ |
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debug("[ sii: command INXFER to scsiid=%i ]\n", |
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d->siiregs.slcsr); |
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if (d->siiregs.comm & SII_DMA) |
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debug("[ sii DMA: TODO ]\n"); |
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else { |
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debug("[ sii: transmitting byte 0x%02x using " |
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"PIO mode ]\n", d->siiregs.data); |
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d->siiregs.comm &= ~SII_INXFER; |
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|
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/* d->siiregs.dstat |= SII_DNE; */ |
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/* Done, only for DMA? */ |
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d->siiregs.dstat |= SII_TBE; /* Buffer empty? */ |
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} |
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} |
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|
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combine_sii_bits(d); |
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|
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if (d->siiregs.csr & SII_IE && d->siiregs.cstat & (SII_CI | SII_DI)) |
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INTERRUPT_ASSERT(d->irq); |
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else |
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INTERRUPT_DEASSERT(d->irq); |
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} |
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|
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|
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DEVICE_ACCESS(sii) |
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{ |
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uint64_t idata = 0, odata = 0; |
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int regnr; |
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struct sii_data *d = extra; |
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|
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if (relative_addr & 3) { |
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debug("[ sii relative_addr = 0x%x !!! ]\n", |
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(int) relative_addr); |
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return 0; |
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} |
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|
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dev_sii_tick(cpu, extra); |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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regnr = relative_addr / 2; |
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odata = d->regs[regnr]; |
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|
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switch (relative_addr) { |
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case 0x00: /* SII_SDB: Diagnostic */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from SDB (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to SDB (data=0x%04x) ]\n", |
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(int)idata); |
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d->regs[regnr] = idata; |
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return 1; |
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} |
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break; |
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case 0x0c: /* SII_CSR: Control/status */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from CSR (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to CSR (data=0x%04x: %s %s " |
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"%s %s %s) ]\n", (int)idata, |
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idata & SII_HPM? "HPM" : "!hpm", |
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idata & SII_RSE? "RSE" : "!rse", |
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idata & SII_SLE? "SLE" : "!sle", |
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idata & SII_PCE? "PCE" : "!pce", |
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idata & SII_IE? "IE" : "!ie"); |
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d->regs[regnr] = idata; |
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return 1; |
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} |
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break; |
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case 0x10: /* SII_ID: SCSI ID */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from ID (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to ID (data=0x%04x: scsi id %i)" |
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" ]\n", (int)idata, (int)(idata & 7)); |
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if (!(idata & SII_ID_IO)) |
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debug("WARNING: sii ID bit SII_ID_IO not " |
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"set on write!\n"); |
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idata &= ~SII_ID_IO; |
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if ((idata & ~0x7) != 0) |
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debug("WARNING: sii ID bits that should " |
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"be zero are not zero!\n"); |
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idata &= 0x7; |
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d->regs[regnr] = idata & 0x7; |
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return 1; |
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} |
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break; |
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case 0x14: /* SII_SLCSR: Selector control */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from SLCSR (data=0x%04x: " |
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"scsi_id=%i) ]\n", d->regs[regnr], |
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d->regs[regnr] & 7); |
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} else { |
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debug("[ sii: write to SLCSR (data=0x%04x: " |
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"scsi_id=%i) ]\n", (int)idata, (int)(idata & 7)); |
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if ((idata & ~0x7) != 0) |
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debug("WARNING: sii SLCSR bits that should " |
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"be zero are not zero!\n"); |
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idata &= 0x7; |
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d->regs[regnr] = idata & 0x7; |
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return 1; |
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} |
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break; |
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case 0x18: /* SII_DESTAT: Selection detector status */ |
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if (writeflag == MEM_READ) { |
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/* TODO: set DESTAT from somewhere else? */ |
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debug("[ sii: read from DESTAT (data=0x%04x: " |
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"scsi_id=%i) ]\n", d->regs[regnr], |
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d->regs[regnr] & 7); |
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} else { |
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debug("[ sii: write to DESTAT (data=0x%04x: " |
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"scsi_id=%i) ]\n", (int)idata, (int)(idata & 7)); |
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debug("WARNING: sii DESTAT is read-only!\n"); |
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return 1; |
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} |
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break; |
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case 0x20: /* SII_DATA: Data register */ |
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if (writeflag == MEM_READ) { |
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/* TODO */ |
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debug("[ sii: read from DATA (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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/* TODO */ |
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debug("[ sii: write to DATA (data=0x%04x) ]\n", |
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(int)idata); |
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idata &= 0xff; |
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d->regs[regnr] = idata; |
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return 1; |
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} |
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break; |
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case 0x24: /* SII_DMCTRL: DMA control */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from DMCTRL (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to DMCTRL (data=0x%04x: %s) ]\n", |
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(int)idata, (idata & 3)==0? "async" : "sync"); |
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if ((idata & ~0x3) != 0) |
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debug("WARNING: sii DMCTRL bits that " |
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"should be zero are not zero!\n"); |
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idata &= 0x3; |
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d->regs[regnr] = idata; |
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return 1; |
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} |
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break; |
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case 0x48: /* SII_CSTAT: Connection status */ |
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if (writeflag == MEM_READ) { |
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debug("[ sii: read from CSTAT (data=0x%04x) ]\n", |
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d->regs[regnr]); |
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} else { |
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debug("[ sii: write to CSTAT (data=0x%04x) ]\n", |
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(int)idata); |
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|
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/* readonly / writeoncetoclear bits according |
| 312 |
to page 21 in the DS3100 manual: */ |
| 313 |
if (idata & (1<<13)) { |
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idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13); |
| 315 |
} |
| 316 |
if (idata & (1<<12)) { |
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idata &= ~(1<<12); d->regs[regnr] &= ~(1<<12); |
| 318 |
} |
| 319 |
if (idata & (1<<11)) { |
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/* is this actually write-1-to-clear? */ |
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idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11); |
| 322 |
} |
| 323 |
if (idata & (1<<9)) { |
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/* ? */ |
| 325 |
idata &= ~(1<<9); d->regs[regnr] &= ~(1<<9); |
| 326 |
} |
| 327 |
if (idata & (1<<8)) { |
| 328 |
/* ? */ |
| 329 |
idata &= ~(1<<8); d->regs[regnr] &= ~(1<<8); |
| 330 |
} |
| 331 |
if (idata & (1<<7)) { |
| 332 |
idata &= ~(1<<7); d->regs[regnr] &= ~(1<<7); |
| 333 |
} |
| 334 |
if (idata & (1<<3)) { |
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idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3); |
| 336 |
} |
| 337 |
|
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/* Read-only bits are taken from the old register: */ |
| 339 |
idata &= ~0x3bf7; |
| 340 |
idata |= d->regs[regnr] & 0x3bf7; |
| 341 |
|
| 342 |
d->regs[regnr] = idata; |
| 343 |
return 1; |
| 344 |
} |
| 345 |
break; |
| 346 |
case 0x4c: /* SII_DSTAT: Data transfer status */ |
| 347 |
if (writeflag == MEM_READ) { |
| 348 |
debug("[ sii: read from DSTAT (data=0x%04x) ]\n", |
| 349 |
d->regs[regnr]); |
| 350 |
} else { |
| 351 |
debug("[ sii: write to DSTAT (data=0x%04x) ]\n", |
| 352 |
(int)idata); |
| 353 |
|
| 354 |
/* readonly / writeoncetoclear bits |
| 355 |
according to page 22 in the DS3100 manual: */ |
| 356 |
if (idata & (1<<13)) { |
| 357 |
idata &= ~(1<<13); d->regs[regnr] &= ~(1<<13); |
| 358 |
} |
| 359 |
if (idata & (1<<11)) { |
| 360 |
/* is this write-1-to-clear? */ |
| 361 |
idata &= ~(1<<11); d->regs[regnr] &= ~(1<<11); |
| 362 |
} |
| 363 |
if (idata & (1<<10)) { |
| 364 |
/* is this write-1-to-clear? */ |
| 365 |
idata &= ~(1<<10); d->regs[regnr] &= ~(1<<10); |
| 366 |
} |
| 367 |
if (idata & (1<<4)) { |
| 368 |
/* is this write-1-to-clear? */ |
| 369 |
idata &= ~(1<<4); d->regs[regnr] &= ~(1<<4); |
| 370 |
} |
| 371 |
if (idata & (1<<3)) { |
| 372 |
idata &= ~(1<<3); d->regs[regnr] &= ~(1<<3); |
| 373 |
} |
| 374 |
|
| 375 |
/* Read-only bits are taken from the old register: */ |
| 376 |
idata &= ~0x0c17; |
| 377 |
idata |= d->regs[regnr] & 0x0c17; |
| 378 |
|
| 379 |
d->regs[regnr] = idata; |
| 380 |
return 1; |
| 381 |
} |
| 382 |
break; |
| 383 |
case 0x50: /* SII_COMM: Command */ |
| 384 |
if (writeflag == MEM_READ) { |
| 385 |
debug("[ sii: read from COMM (data=0x%04x) ]\n", |
| 386 |
d->regs[regnr]); |
| 387 |
} else { |
| 388 |
debug("[ sii: write to COMM (data=0x%04x: %s %s " |
| 389 |
"%s command=0x%02x rest=0x%02x) ]\n", (int)idata, |
| 390 |
idata & SII_DMA? "DMA" : "!dma", |
| 391 |
idata & SII_DO_RST? "RST" : "!rst", |
| 392 |
idata & SII_RSL? "RSL" : "!rsl", |
| 393 |
/* command, 5 bits: */ |
| 394 |
(int)((idata >> 7) & 0x1f), |
| 395 |
/* rest, 7 bits: */ |
| 396 |
(int)(idata & 0x3f)); |
| 397 |
|
| 398 |
if (idata & SII_DO_RST) { |
| 399 |
/* Reset: TODO */ |
| 400 |
} |
| 401 |
|
| 402 |
idata &= ~SII_DO_RST; |
| 403 |
d->regs[regnr] = idata; |
| 404 |
|
| 405 |
dev_sii_tick(cpu, extra); |
| 406 |
return 1; |
| 407 |
} |
| 408 |
break; |
| 409 |
case 0x54: /* SII_DICTRL: Diagnostics control */ |
| 410 |
if (writeflag == MEM_READ) { |
| 411 |
debug("[ sii: read from DICTRL (data=0x%04x) ]\n", |
| 412 |
d->regs[regnr]); |
| 413 |
} else { |
| 414 |
debug("[ sii: write to DICTRL (data=0x%04x: " |
| 415 |
"port=%s) ]\n", (int)idata, |
| 416 |
idata & SII_PRE? "enabled" : "disabled"); |
| 417 |
if ((idata & ~0xf) != 0) |
| 418 |
debug("WARNING: sii DICTRL bits that " |
| 419 |
"should be zero are not zero!\n"); |
| 420 |
d->regs[regnr] = idata; |
| 421 |
return 1; |
| 422 |
} |
| 423 |
break; |
| 424 |
default: |
| 425 |
if (writeflag==MEM_READ) { |
| 426 |
debug("[ sii: read from %08lx (data=0x%04x) ]\n", |
| 427 |
(long)relative_addr, d->regs[regnr]); |
| 428 |
} else { |
| 429 |
debug("[ sii: write to %08lx (data=0x%04x) ]\n", |
| 430 |
(long)relative_addr, (int)idata); |
| 431 |
d->regs[regnr] = idata; |
| 432 |
} |
| 433 |
} |
| 434 |
|
| 435 |
if (writeflag == MEM_READ) |
| 436 |
memory_writemax64(cpu, data, len, odata); |
| 437 |
|
| 438 |
return 1; |
| 439 |
} |
| 440 |
|
| 441 |
|
| 442 |
void dev_sii_init(struct machine *machine, struct memory *mem, |
| 443 |
uint64_t baseaddr, uint64_t buf_start, uint64_t buf_end, |
| 444 |
char *irq_path) |
| 445 |
{ |
| 446 |
struct sii_data *d; |
| 447 |
|
| 448 |
CHECK_ALLOCATION(d = malloc(sizeof(struct sii_data))); |
| 449 |
memset(d, 0, sizeof(struct sii_data)); |
| 450 |
|
| 451 |
INTERRUPT_CONNECT(irq_path, d->irq); |
| 452 |
d->buf_start = buf_start; |
| 453 |
d->buf_end = buf_end; |
| 454 |
d->regs = (uint16_t *) &d->siiregs; |
| 455 |
|
| 456 |
memory_device_register(mem, "sii", baseaddr, DEV_SII_LENGTH, |
| 457 |
dev_sii_access, (void *)d, DM_DEFAULT, NULL); |
| 458 |
|
| 459 |
machine_add_tickfunction(machine, dev_sii_tick, d, |
| 460 |
SII_TICK_SHIFT); |
| 461 |
} |
| 462 |
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