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/* |
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* Copyright (C) 2006-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_lca.c,v 1.10 2007/06/15 19:11:15 debug Exp $ |
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* |
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* COMMENT: LCA PCI bus, for Alpha machines |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "bus_isa.h" |
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#include "bus_pci.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "emul.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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#include "alpha_lcareg.h" |
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|
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#define LCA_ISA_BASE (LCA_PCI_SIO + 0x10000000) |
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#define LCA_ISA_MEMBASE (LCA_PCI_SIO + 0x18000000) |
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|
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|
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struct lca_data { |
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struct pci_data *pci_data; |
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|
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uint64_t ioc_conf; |
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uint64_t tlb_enable; |
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uint64_t window_base_0; |
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uint64_t window_mask_0; |
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uint64_t window_t_base_0; |
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uint64_t window_base_1; |
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uint64_t window_mask_1; |
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uint64_t window_t_base_1; |
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}; |
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|
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|
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/* |
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* lca_interrupt_assert(): |
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* |
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* Line 0 = ISA interrupt. |
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*/ |
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void lca_interrupt_assert(struct interrupt *interrupt) |
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{ |
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fatal("lca_interrupt_assert: TODO\n"); |
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exit(1); |
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} |
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|
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|
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/* |
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* lca_interrupt_deassert(): |
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* |
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* Line 0 = ISA interrupt. |
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*/ |
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void lca_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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fatal("lca_interrupt_deassert: TODO\n"); |
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exit(1); |
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} |
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|
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|
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DEVICE_ACCESS(lca_pci_conf) |
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{ |
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uint64_t idata = 0, odata = 0; |
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int tag, bus, dev, func, reg; |
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struct lca_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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/* |
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* 1. Decompose the address into a tag. |
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* |
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* According to NetBSD's lca_pci.c, the address is composed like this: |
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* |
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* addr = tag << 5 | (regoffset & ~0x03) << 5 | 0x3 << 3 |
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*/ |
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reg = (relative_addr >> 5) & 0xfc; |
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tag = (relative_addr >> 5) & ~0xff; |
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|
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/* |
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* 2. Decompose the tag into bus, dev, and func. |
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* |
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* The tag can be constructed in one of two ways. On the primary |
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* bus (nr 0): |
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* |
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* tag = (1 << (device + 11)) | (function << 8); |
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* |
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* and on other busses, the tag is a normal: |
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* |
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* tag = (bus << 16) | (device << 11) | (function << 8) |
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*/ |
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/* printf("tag = 0x%x\n", (int)tag); */ |
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bus = d->ioc_conf & 1; |
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|
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if (bus == 0) { |
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for (dev=0; dev<21; dev++) |
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if (tag & (0x800 << dev)) |
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break; |
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if (dev >= 21) { |
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/* fatal("[ LCA: No bus 0 device? TODO ]\n"); |
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exit(1); */ |
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dev = 0; |
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} |
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} else { |
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fatal("TODO. Non-zero bus.\n"); |
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exit(1); |
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} |
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|
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func = (tag >> 8) & 7; |
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/* printf("bus=%i dev=%i func=%i reg=%i\n", bus,dev,func,reg); */ |
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|
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/* Pass PCI accesses onto bus_pci: */ |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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&odata : &idata, len, writeflag); |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVICE_ACCESS(lca_isa) |
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{ |
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unsigned int ofs, i; |
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uint8_t byte; |
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|
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relative_addr >>= 5; |
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|
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ofs = relative_addr & 3; |
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if (ofs > len) { |
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fatal("[ ofs=%i len=%i in lca_isa access function. " |
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"aborting ]\n", ofs, len); |
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exit(1); |
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} |
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|
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if (writeflag == MEM_WRITE) { |
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byte = data[ofs % len]; |
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return cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE + |
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relative_addr, &byte, 1, writeflag, CACHE_NONE); |
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} |
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|
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cpu->memory_rw(cpu, cpu->mem, LCA_ISA_BASE + relative_addr, |
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&byte, 1, MEM_READ, CACHE_NONE); |
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|
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for (i=0; i<len; i++) |
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data[i] = i == ofs? byte : 0x00; |
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|
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return 1; |
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} |
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|
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|
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DEVICE_ACCESS(lca_ioc) |
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{ |
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uint64_t idata = 0, odata = 0; |
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struct lca_data *d = extra; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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switch (relative_addr + LCA_IOC_BASE) { |
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|
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case LCA_IOC_BASE: |
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/* Ignore? Linux reads from the base at startup. */ |
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break; |
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|
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case LCA_IOC_CONF: |
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if (writeflag == MEM_READ) { |
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odata = d->ioc_conf; |
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} else { |
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d->ioc_conf = idata; |
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/* Only bit 0 is implemented so far, the PCI bus 0 vs |
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bus non-0 selection bit. */ |
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if (idata & ~1) { |
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fatal("TODO: Write to unimplemented bit of" |
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" IOC_CONF: 0x%x\n", (int)idata); |
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exit(1); |
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} |
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} |
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break; |
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|
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case LCA_IOC_TBIA: |
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/* TLB Invalidate All. */ |
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/* TODO: For now, let's just ignore it. */ |
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break; |
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|
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case LCA_IOC_TB_ENA: |
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if (writeflag == MEM_READ) { |
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odata = d->tlb_enable; |
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} else { |
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d->tlb_enable = idata; |
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/* TODO: Actually implement this. */ |
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if (idata & ~IOC_TB_ENA_TEN) { |
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fatal("TODO: LCA_IOC_TB_ENA value " |
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" (0x%"PRIx64") has unimplemented " |
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"bits.\n", (uint64_t)idata); |
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exit(1); |
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} |
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} |
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break; |
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|
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case LCA_IOC_W_BASE0: |
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if (writeflag == MEM_READ) { |
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odata = d->window_base_0; |
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} else { |
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d->window_base_0 = idata; |
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/* TODO: Actually implement this. */ |
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if (idata != 0ULL && idata != 0x300800000ULL) { |
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fatal("TODO: LCA_IOC_W_BASE0 value differs" |
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" (0x%"PRIx64") from the only implemented" |
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" values\n", (uint64_t)idata); |
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exit(1); |
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} |
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} |
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break; |
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|
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case LCA_IOC_W_MASK0: |
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if (writeflag == MEM_READ) { |
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odata = d->window_mask_0; |
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} else { |
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d->window_mask_0 = idata; |
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/* TODO: Actually implement this. */ |
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if (idata != 0x700000ULL) { |
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fatal("TODO: LCA_IOC_W_MASK0 value differs" |
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" (0x%"PRIx64") from the only implemented" |
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" value\n", (uint64_t)idata); |
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exit(1); |
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} |
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} |
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break; |
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|
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case LCA_IOC_W_T_BASE0: |
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if (writeflag == MEM_READ) { |
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odata = d->window_t_base_0; |
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} else { |
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d->window_t_base_0 = idata; |
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/* TODO: Actually implement this. */ |
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} |
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break; |
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|
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case LCA_IOC_W_BASE1: |
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if (writeflag == MEM_READ) { |
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odata = d->window_base_1; |
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} else { |
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d->window_base_1 = idata; |
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/* TODO: Actually implement this. */ |
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if (idata != 0x240000000ULL) { |
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fatal("TODO: LCA_IOC_W_BASE1 value differs" |
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" (0x%"PRIx64") from the only implemented" |
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" value\n", (uint64_t)idata); |
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exit(1); |
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} |
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} |
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break; |
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|
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case LCA_IOC_W_MASK1: |
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if (writeflag == MEM_READ) { |
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odata = d->window_mask_1; |
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} else { |
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d->window_mask_1 = idata; |
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/* TODO: Actually implement this. */ |
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if (idata != 0x3ff00000ULL) { |
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fatal("TODO: LCA_IOC_W_MASK1 value differs" |
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" (0x%"PRIx64") from the only implemented" |
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" value\n", (uint64_t)idata); |
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exit(1); |
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} |
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} |
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break; |
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|
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case LCA_IOC_W_T_BASE1: |
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if (writeflag == MEM_READ) { |
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odata = d->window_t_base_1; |
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} else { |
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d->window_t_base_1 = idata; |
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/* TODO: Actually implement this. */ |
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} |
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break; |
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|
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default:fatal("[ lca_ioc: unimplemented %s to offset 0x%x", |
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writeflag == MEM_WRITE? "write" : "read", (int) |
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relative_addr); |
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if (writeflag == MEM_WRITE) |
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fatal(": 0x%x", (int)idata); |
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fatal(" ]\n"); |
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exit(1); |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(lca) |
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{ |
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char *interrupt_path; |
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struct interrupt interrupt_template; |
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struct lca_data *d; |
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|
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CHECK_ALLOCATION(d = malloc(sizeof(struct lca_data))); |
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memset(d, 0, sizeof(struct lca_data)); |
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|
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/* Register a PCI bus: */ |
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d->pci_data = bus_pci_init( |
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devinit->machine, |
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"TODO: irq" /* pciirq: TODO */, |
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LCA_PCI_SIO, /* pci device io offset */ |
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0x00000000, /* pci device mem offset: TODO */ |
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0x00000000, /* PCI portbase: TODO */ |
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0x00000000, /* PCI membase: TODO */ |
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"TODO: pci irq base", /* PCI irqbase: TODO */ |
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LCA_ISA_BASE, /* ISA portbase */ |
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LCA_ISA_MEMBASE, /* ISA membase */ |
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"TODO: irqbase isa"); /* ISA irqbase: TODO */ |
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|
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/* Add the "sio0" controller (as seen by NetBSD): */ |
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bus_pci_add(devinit->machine, d->pci_data, devinit->machine->memory, |
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0, 7, 0, "i82378zb"); |
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|
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memory_device_register(devinit->machine->memory, "lca_pci_conf", |
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LCA_PCI_CONF, 0x20000000, dev_lca_pci_conf_access, (void *)d, |
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DM_DEFAULT, NULL); |
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|
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memory_device_register(devinit->machine->memory, "lca_isa", |
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LCA_PCI_SIO, 0x10000 << 5, dev_lca_isa_access, (void *)d, |
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DM_DEFAULT, NULL); |
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|
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memory_device_register(devinit->machine->memory, "lca_ioc", |
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LCA_IOC_BASE, 0x20000000, dev_lca_ioc_access, (void *)d, |
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DM_DEFAULT, NULL); |
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|
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CHECK_ALLOCATION(interrupt_path = |
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malloc(strlen(devinit->machine->path) + 10)); |
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snprintf(interrupt_path, strlen(devinit->machine->path) + 10, |
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"%s.lca", devinit->machine->path); |
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|
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memset(&interrupt_template, 0, sizeof(interrupt_template)); |
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interrupt_template.line = 0; |
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interrupt_template.name = interrupt_path; |
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interrupt_template.extra = d; |
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interrupt_template.interrupt_assert = lca_interrupt_assert; |
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interrupt_template.interrupt_deassert = lca_interrupt_deassert; |
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interrupt_handler_register(&interrupt_template); |
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|
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bus_isa_init(devinit->machine, interrupt_path, |
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BUS_ISA_IDE0 | BUS_ISA_IDE1, LCA_ISA_BASE, LCA_ISA_MEMBASE); |
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|
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return 1; |
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} |
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