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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_kn02.c,v 1.28 2007/06/15 19:11:15 debug Exp $ |
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* |
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* COMMENT: DEC KN02 mainbus (TurboChannel interrupt controller) |
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* |
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* Used in DECstation type 2 ("3MAX"). See include/dec_kn02.h for more info. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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#include "dec_kn02.h" |
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|
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#define DEV_KN02_LENGTH 0x1000 |
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|
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|
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struct kn02_data { |
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uint8_t csr[sizeof(uint32_t)]; |
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|
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/* Dummy fill bytes, so dyntrans can be used: */ |
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uint8_t filler[DEV_KN02_LENGTH - sizeof(uint32_t)]; |
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|
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struct interrupt irq; |
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int int_asserted; |
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}; |
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|
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|
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/* |
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* kn02_interrupt_assert(), kn02_interrupt_deassert(): |
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* |
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* Called whenever a KN02 (TurboChannel) interrupt is asserted/deasserted. |
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*/ |
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void kn02_interrupt_assert(struct interrupt *interrupt) |
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{ |
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struct kn02_data *d = interrupt->extra; |
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d->csr[0] |= interrupt->line; |
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if (d->csr[0] & d->csr[2] && !d->int_asserted) { |
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d->int_asserted = 1; |
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INTERRUPT_ASSERT(d->irq); |
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} |
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} |
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void kn02_interrupt_deassert(struct interrupt *interrupt) |
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{ |
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struct kn02_data *d = interrupt->extra; |
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d->csr[0] &= ~interrupt->line; |
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if (!(d->csr[0] & d->csr[2]) && d->int_asserted) { |
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d->int_asserted = 0; |
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INTERRUPT_DEASSERT(d->irq); |
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} |
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} |
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|
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|
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DEVICE_ACCESS(kn02) |
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{ |
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struct kn02_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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switch (relative_addr) { |
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case 0: |
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if (writeflag==MEM_READ) { |
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odata = d->csr[0] + (d->csr[1] << 8) + |
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(d->csr[2] << 16) + (d->csr[3] << 24); |
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|
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/* debug("[ kn02: read from CSR: 0x%08x ]\n", odata); */ |
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} else { |
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/* |
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* Only bits 23..8 are considered writable. The |
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* lowest 8 bits are actually writable, but don't |
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* affect the interrupt I/O bits; the low 8 bits |
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* on write turn on and off LEDs. (There are no |
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* LEDs in the emulator, so those bits are just |
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* ignored.) |
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*/ |
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int old_assert = (d->csr[0] & d->csr[2])? 1 : 0; |
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int new_assert; |
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/* fatal("[ kn02: write to CSR: 0x%08x ]\n", idata); */ |
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|
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d->csr[1] = (idata >> 8) & 255; |
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d->csr[2] = (idata >> 16) & 255; |
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|
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/* Recalculate interrupt assertions: */ |
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new_assert = (d->csr[0] & d->csr[2])? 1 : 0; |
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if (new_assert != old_assert) { |
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if (new_assert) { |
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INTERRUPT_ASSERT(d->irq); |
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d->int_asserted = 1; |
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} else { |
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INTERRUPT_DEASSERT(d->irq); |
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d->int_asserted = 0; |
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} |
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} |
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} |
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break; |
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default: |
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if (writeflag==MEM_READ) { |
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debug("[ kn02: read from 0x%08lx ]\n", |
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(long)relative_addr); |
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} else { |
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debug("[ kn02: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, (int)idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(kn02) |
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{ |
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struct kn02_data *d; |
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uint32_t csr; |
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int i; |
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|
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CHECK_ALLOCATION(d = malloc(sizeof(struct kn02_data))); |
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memset(d, 0, sizeof(struct kn02_data)); |
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|
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/* Connect the KN02 to a specific MIPS CPU interrupt line: */ |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
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|
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/* Register the 8 possible TurboChannel interrupts: */ |
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for (i=0; i<8; i++) { |
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struct interrupt template; |
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char tmpstr[300]; |
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snprintf(tmpstr, sizeof(tmpstr), "%s.kn02.%i", |
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devinit->interrupt_path, i); |
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memset(&template, 0, sizeof(template)); |
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template.line = 1 << i; |
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template.name = tmpstr; |
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template.extra = d; |
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template.interrupt_assert = kn02_interrupt_assert; |
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template.interrupt_deassert = kn02_interrupt_deassert; |
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interrupt_handler_register(&template); |
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} |
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|
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/* |
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* Set initial value of the CSR. Note: If the KN02_CSR_NRMMOD bit |
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* is not set, the 5000/200 PROM image loops forever. |
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*/ |
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csr = KN02_CSR_NRMMOD; |
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d->csr[0] = csr; |
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d->csr[1] = csr >> 8; |
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d->csr[2] = csr >> 16; |
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d->csr[3] = csr >> 24; |
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|
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memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_KN02_LENGTH, dev_kn02_access, d, |
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DM_DYNTRANS_OK, &d->csr[0]); |
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|
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return 1; |
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} |
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