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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_eagle.c,v 1.19 2007/06/15 19:11:15 debug Exp $ |
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* |
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* COMMENT: Motorola MPC105 "Eagle" host bridge |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "bus_isa.h" |
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#include "bus_pci.h" |
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#include "cpu.h" |
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#include "device.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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struct eagle_data { |
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struct interrupt irq; |
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|
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struct pci_data *pci_data; |
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}; |
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|
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|
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DEVICE_ACCESS(eagle) |
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{ |
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struct eagle_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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int bus, dev, func, reg; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN); |
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|
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/* |
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* Pass accesses to ISA ports 0xcf8 and 0xcfc onto bus_pci_*: |
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*/ |
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|
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switch (relative_addr) { |
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|
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case 0: /* Address: */ |
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bus_pci_decompose_1(idata, &bus, &dev, &func, ®); |
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bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg); |
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break; |
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|
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case 4: /* Data: */ |
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bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ? |
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&odata : &idata, len, writeflag); |
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break; |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(eagle) |
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{ |
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struct eagle_data *d; |
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uint64_t pci_io_offset, pci_mem_offset; |
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uint64_t isa_portbase = 0, isa_membase = 0; |
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uint64_t pci_portbase = 0, pci_membase = 0; |
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char pci_irq_base[300]; |
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char isa_irq_base[300]; |
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|
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CHECK_ALLOCATION(d = malloc(sizeof(struct eagle_data))); |
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memset(d, 0, sizeof(struct eagle_data)); |
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|
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/* The interrupt path to the CPU at which we are connected: */ |
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INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
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|
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/* |
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* According to http://www.beatjapan.org/mirror/www.be.com/ |
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* aboutbe/benewsletter/Issue27.html#Cookbook : |
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* |
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* "HARDWARE MEMORY MAP |
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* The MPC105 defines the physical memory map of the system as |
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* follows: |
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* |
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* Start Size Description |
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* |
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* 0x00000000 0x40000000 Physical RAM |
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* 0x40000000 0x40000000 Other system memory |
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* (motherboard glue regs) |
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* 0x80000000 0x00800000 ISA I/O |
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* 0x81000000 0x3E800000 PCI I/O |
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* 0xBFFFFFF0 0x00000010 PCI/ISA interrupt acknowledge |
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* 0xC0000000 0x3F000000 PCI memory |
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* 0xFF000000 0x01000000 ROM/flash |
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*/ |
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|
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/* TODO: Make these work like the BE web page stated... */ |
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pci_io_offset = 0x80000000ULL; |
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pci_mem_offset = 0xc0000000ULL; |
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pci_portbase = 0x00000000ULL; |
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pci_membase = 0x00000000ULL; |
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isa_portbase = 0x80000000ULL; |
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isa_membase = 0xc0000000ULL; |
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|
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switch (devinit->machine->machine_type) { |
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case MACHINE_BEBOX: |
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snprintf(pci_irq_base, sizeof(pci_irq_base), "%s.bebox", |
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devinit->interrupt_path); |
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snprintf(isa_irq_base, sizeof(isa_irq_base), "%s.bebox.5", |
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devinit->interrupt_path); |
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break; |
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default: |
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snprintf(pci_irq_base, sizeof(pci_irq_base), "%s", |
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devinit->interrupt_path); |
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snprintf(isa_irq_base, sizeof(isa_irq_base), "%s", |
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devinit->interrupt_path); |
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} |
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|
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/* Create a PCI bus: */ |
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d->pci_data = bus_pci_init(devinit->machine, devinit->interrupt_path, |
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pci_io_offset, pci_mem_offset, |
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pci_portbase, pci_membase, pci_irq_base, |
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isa_portbase, isa_membase, isa_irq_base); |
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|
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/* Add the PCI glue for the controller itself: */ |
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bus_pci_add(devinit->machine, d->pci_data, |
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devinit->machine->memory, 0, 0, 0, "eagle"); |
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|
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/* ADDR and DATA configuration ports in ISA space: */ |
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memory_device_register(devinit->machine->memory, "eagle", |
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isa_portbase + BUS_PCI_ADDR, 8, dev_eagle_access, d, |
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DM_DEFAULT, NULL); |
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|
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switch (devinit->machine->machine_type) { |
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|
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case MACHINE_BEBOX: |
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bus_isa_init(devinit->machine, isa_irq_base, |
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BUS_ISA_IDE0 | BUS_ISA_VGA, isa_portbase, isa_membase); |
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bus_pci_add(devinit->machine, d->pci_data, |
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devinit->machine->memory, 0, 11, 0, "i82378zb"); |
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break; |
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|
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case MACHINE_PREP: |
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bus_pci_add(devinit->machine, d->pci_data, |
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devinit->machine->memory, 0, 11, 0, "ibm_isa"); |
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break; |
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|
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case MACHINE_MVMEPPC: |
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bus_isa_init(devinit->machine, isa_irq_base, |
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BUS_ISA_LPTBASE_3BC, isa_portbase, isa_membase); |
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|
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switch (devinit->machine->machine_subtype) { |
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case MACHINE_MVMEPPC_1600: |
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bus_pci_add(devinit->machine, d->pci_data, |
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devinit->machine->memory, 0, 11, 0, "i82378zb"); |
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break; |
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default:fatal("unimplemented machine subtype for " |
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"eagle/mvmeppc\n"); |
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exit(1); |
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} |
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break; |
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|
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default:fatal("unimplemented machine type for eagle\n"); |
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exit(1); |
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} |
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|
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devinit->return_ptr = d->pci_data; |
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|
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return 1; |
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} |
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