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/* |
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* Copyright (C) 2006-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_dreamcast_g2.c,v 1.5 2007/06/15 19:11:15 debug Exp $ |
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* |
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* COMMENT: Dreamcast G2 bus |
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* |
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* Register offsets are from KOS, NetBSD sources, etc. |
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* |
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* TODO: |
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* Figure out what all these registers do! |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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#ifdef UNSTABLE_DEVEL |
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#define debug fatal |
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#endif |
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|
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#define NREGS (0x100/sizeof(uint32_t)) |
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|
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struct dreamcast_g2_data { |
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uint32_t dma_reg[NREGS]; |
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uint32_t extdma_reg[NREGS]; |
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uint32_t unknown_reg[NREGS]; |
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}; |
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|
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/* dma_reg[] offsets: */ |
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#define PVR_STATE 0x00 |
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#define PVR_LEN 0x04 |
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#define PVR_DST 0x08 |
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#define PVR_LMMODE0 0x84 |
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#define PVR_LMMODE1 0x88 |
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|
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/* |
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* External DMA: 4 channels |
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* |
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* Note: Addresses and sizes must be 32-byte aligned. |
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* DIR is 0 for CPU to External device, 1 for External to CPU. |
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* MODE should be 5 for transfers to/from the SPU. |
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*/ |
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#define EXTDMA_CTRL_EXT_ADDR 0x00 /* EXTDMA_CTRL_* are repeated */ |
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#define EXTDMA_CTRL_SH4_ADDR 0x04 /* 4 times (once for each channel) */ |
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#define EXTDMA_CTRL_SIZE 0x08 |
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#define EXTDMA_CTRL_DIR 0x0c |
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#define EXTDMA_CTRL_MODE 0x10 |
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#define EXTDMA_CTRL_CTRL1 0x14 |
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#define EXTDMA_CTRL_CTRL2 0x18 |
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#define EXTDMA_CTRL_UNKNOWN 0x1c |
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|
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#define EXTDMA_WAITSTATE 0x90 |
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#define EXTDMA_MAGIC 0xbc |
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#define EXTDMA_MAGIC_VALUE 0x4659404f |
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|
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#define EXTDMA_STAT_EXT_ADDR 0xc0 /* EXTDMA_STAT_* are repeated 4 */ |
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#define EXTDMA_STAT_SH4_ADDR 0xc4 /* times too */ |
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#define EXTDMA_STAT_SIZE 0xc8 |
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#define EXTDMA_STAT_STATUS 0xcc |
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|
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|
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DEVICE_ACCESS(dreamcast_g2) |
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{ |
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struct dreamcast_g2_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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/* Default read: */ |
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if (writeflag == MEM_READ) |
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odata = d->dma_reg[relative_addr / sizeof(uint32_t)]; |
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|
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switch (relative_addr) { |
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|
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case PVR_LMMODE0: /* 0x84 */ |
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case PVR_LMMODE1: /* 0x88 */ |
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if (writeflag == MEM_WRITE) { |
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if (idata == 0) { |
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/* Done by IP.BIN during startup... */ |
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} else { |
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fatal("[ dreamcast_g2: UNIMPLEMENTED write " |
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"0x84/0x88: TODO ]\n"); |
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exit(1); |
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} |
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} else { |
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fatal("[ dreamcast_g2: read from 0x84/0x88: TODO ]\n"); |
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exit(1); |
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} |
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break; |
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|
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case 0x8c: |
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if (writeflag == MEM_WRITE) { |
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fatal("[ dreamcast_g2: write to 0x8c: TODO ]\n"); |
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exit(1); |
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} else { |
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/* 0x20 means G2 DMA in progress? */ |
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/* 0x11 = mask which has to do with AICA */ |
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odata = 0x11 * (random() & 1); |
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} |
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break; |
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|
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default:if (writeflag == MEM_READ) { |
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fatal("[ dreamcast_g2: read from addr 0x%x ]\n", |
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(int)relative_addr); |
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} else { |
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fatal("[ dreamcast_g2: write to addr 0x%x: 0x%x ]\n", |
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(int)relative_addr, (int)idata); |
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} |
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exit(1); |
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} |
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|
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/* Default write: */ |
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if (writeflag == MEM_WRITE) |
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d->dma_reg[relative_addr / sizeof(uint32_t)] = idata; |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVICE_ACCESS(dreamcast_g2_extdma) |
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{ |
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struct dreamcast_g2_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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int reg = relative_addr, channel = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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/* Default read: */ |
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if (writeflag == MEM_READ) |
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odata = d->extdma_reg[relative_addr / sizeof(uint32_t)]; |
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|
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if (reg < 0x7f) { |
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channel = (reg >> 5) & 3; |
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reg &= 0x1f; |
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} |
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|
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if (reg >= 0xc0 && reg < 0xff) { |
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channel = (reg >> 4) & 3; |
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reg = 0xc0 + (reg & 0xf); |
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} |
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|
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switch (reg) { |
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|
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case EXTDMA_WAITSTATE: |
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break; |
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|
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case 0x94: |
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/* Written to by boot stage 1 in IP.BIN? */ |
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if (writeflag == MEM_WRITE) { |
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if (idata != 0x271) { |
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fatal("Unimplemented write to extdma 0x94\n"); |
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exit(1); |
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} |
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} |
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break; |
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|
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default:if (writeflag == MEM_READ) { |
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fatal("[ dreamcast_g2_extdma: read from addr 0x%x ]\n", |
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(int)relative_addr); |
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} else { |
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fatal("[ dreamcast_g2_extdma: write to addr 0x%x: " |
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"0x%x ]\n", (int)relative_addr, (int)idata); |
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} |
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exit(1); |
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} |
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|
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/* Default write: */ |
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if (writeflag == MEM_WRITE) |
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d->extdma_reg[relative_addr / sizeof(uint32_t)] = idata; |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVICE_ACCESS(dreamcast_g2_unknown) |
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{ |
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struct dreamcast_g2_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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/* Default read: */ |
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if (writeflag == MEM_READ) |
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odata = d->unknown_reg[relative_addr / sizeof(uint32_t)]; |
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|
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switch (relative_addr) { |
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|
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case 0x90: |
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case 0x94: |
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if (writeflag != MEM_WRITE || idata != 0x222) { |
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fatal("[ dreamcast_g2_unknown: unimplemented 0x90 ]\n"); |
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exit(1); |
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} |
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break; |
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|
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case 0xa0: |
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case 0xa4: |
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if (writeflag != MEM_WRITE || idata != 0x2001) { |
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fatal("[ dreamcast_g2_unknown: unimplemented 0xa0 ]\n"); |
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exit(1); |
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} |
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break; |
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|
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case 0xe4: |
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/* Writing 0x1fffff resets a disabled GD-ROM drive? */ |
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if (writeflag != MEM_WRITE || idata != 0x1fffff) { |
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fatal("[ dreamcast_g2_unknown: unimplemented 0xe4 ]\n"); |
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exit(1); |
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} |
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break; |
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|
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default:if (writeflag == MEM_READ) { |
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fatal("[ dreamcast_g2_unknown: read from addr 0x%x ]\n", |
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(int)relative_addr); |
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} else { |
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fatal("[ dreamcast_g2_unknown: write to addr 0x%x: " |
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"0x%x ]\n", (int)relative_addr, (int)idata); |
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} |
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exit(1); |
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} |
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|
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/* Default write: */ |
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if (writeflag == MEM_WRITE) |
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d->unknown_reg[relative_addr / sizeof(uint32_t)] = idata; |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(dreamcast_g2) |
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{ |
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struct machine *machine = devinit->machine; |
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struct dreamcast_g2_data *d; |
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|
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CHECK_ALLOCATION(d = malloc(sizeof(struct dreamcast_g2_data))); |
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memset(d, 0, sizeof(struct dreamcast_g2_data)); |
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|
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memory_device_register(machine->memory, devinit->name, |
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0x005f6800, 0x100, dev_dreamcast_g2_access, d, DM_DEFAULT, NULL); |
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|
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memory_device_register(machine->memory, devinit->name, 0x005f7800, |
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0x100, dev_dreamcast_g2_extdma_access, d, DM_DEFAULT, NULL); |
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|
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memory_device_register(machine->memory, devinit->name, 0x005f7400, |
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0x100, dev_dreamcast_g2_unknown_access, d, DM_DEFAULT, NULL); |
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|
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return 1; |
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} |
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