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/* |
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* Copyright (C) 2006-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_dreamcast_asic.c,v 1.9 2007/06/15 18:44:19 debug Exp $ |
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* |
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* COMMENT: Dreamcast-specific ASIC |
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* |
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* A simple device which forwards various Dreamcast device events as |
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* interrupts 13, 11, or 9, to the CPU. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <sys/time.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "dreamcast_sysasicvar.h" |
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#include "sh4_exception.h" |
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|
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|
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#define debug fatal |
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|
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#define DREAMCAST_ASIC_TICK_SHIFT 15 |
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|
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struct dreamcast_asic_data { |
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uint32_t pending_irq[3]; |
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uint32_t mask_13[3]; |
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uint32_t mask_11[3]; |
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uint32_t mask_9[3]; |
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|
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int asserted_13; |
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int asserted_11; |
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int asserted_9; |
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|
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struct interrupt irq_13; |
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struct interrupt irq_11; |
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struct interrupt irq_9; |
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}; |
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|
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|
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DEVICE_TICK(dreamcast_asic) |
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{ |
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struct dreamcast_asic_data *d = extra; |
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int i, old_asserted_13 = d->asserted_13, old_asserted_11 = |
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d->asserted_11, old_asserted_9 = d->asserted_9; |
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|
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d->asserted_13 = d->asserted_11 = d->asserted_9 = 0; |
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|
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for (i=0; i<3; i++) { |
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if (d->pending_irq[i] & d->mask_13[i]) |
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d->asserted_13 = 1; |
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|
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if (d->pending_irq[i] & d->mask_11[i]) |
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d->asserted_11 = 1; |
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|
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if (d->pending_irq[i] & d->mask_9[i]) |
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d->asserted_9 = 1; |
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} |
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|
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if (d->asserted_13 != old_asserted_13) { |
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if (d->asserted_13) |
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INTERRUPT_ASSERT(d->irq_13); |
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else |
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INTERRUPT_DEASSERT(d->irq_13); |
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} |
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if (d->asserted_11 != old_asserted_11) { |
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if (d->asserted_11) |
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INTERRUPT_ASSERT(d->irq_11); |
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else |
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INTERRUPT_DEASSERT(d->irq_11); |
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} |
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if (d->asserted_9 != old_asserted_9) { |
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if (d->asserted_9) |
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INTERRUPT_ASSERT(d->irq_9); |
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else |
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INTERRUPT_DEASSERT(d->irq_9); |
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} |
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} |
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|
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|
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DEVICE_ACCESS(dreamcast_asic) |
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{ |
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struct dreamcast_asic_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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int r; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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r = (relative_addr / 4) & 3; |
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if (r == 3) { |
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fatal("[ dreamcast_asic: Bad address ]\n"); |
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r = 0; |
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} |
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|
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switch (relative_addr) { |
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|
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case 0: |
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case 4: |
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case 8: if (writeflag == MEM_READ) { |
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odata = d->pending_irq[r]; |
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} else { |
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/* Should only be used interally by GXemul: */ |
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if (idata & 0x100000000ULL) { |
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/* Set specific bits: */ |
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d->pending_irq[r] |= idata; |
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} else { |
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/* Clear interrupt assertions: */ |
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d->pending_irq[r] &= ~idata; |
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} |
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dev_dreamcast_asic_tick(cpu, d); |
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} |
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break; |
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|
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case 0x10: |
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case 0x14: |
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case 0x18: |
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if (writeflag == MEM_WRITE) { |
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d->mask_13[r] = idata; |
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dev_dreamcast_asic_tick(cpu, d); |
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} else { |
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odata = d->mask_13[r]; |
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} |
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break; |
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|
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case 0x20: |
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case 0x24: |
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case 0x28: |
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if (writeflag == MEM_WRITE) { |
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d->mask_11[r] = idata; |
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dev_dreamcast_asic_tick(cpu, d); |
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} else { |
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odata = d->mask_11[r]; |
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} |
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break; |
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|
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case 0x30: |
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case 0x34: |
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case 0x38: |
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if (writeflag == MEM_WRITE) { |
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d->mask_9[r] = idata; |
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dev_dreamcast_asic_tick(cpu, d); |
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} else { |
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odata = d->mask_9[r]; |
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} |
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break; |
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|
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default:if (writeflag == MEM_READ) { |
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fatal("[ dreamcast_asic: read from addr 0x%x ]\n", |
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(int)relative_addr); |
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} else { |
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fatal("[ dreamcast_asic: write to addr 0x%x: 0x%x ]\n", |
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(int)relative_addr, (int)idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(dreamcast_asic) |
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{ |
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char tmpstr[300]; |
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struct machine *machine = devinit->machine; |
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struct dreamcast_asic_data *d; |
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|
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CHECK_ALLOCATION(d = malloc(sizeof(struct dreamcast_asic_data))); |
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memset(d, 0, sizeof(struct dreamcast_asic_data)); |
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|
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/* Connect to SH4 interrupt levels 13, 11, and 9: */ |
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snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]", |
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devinit->interrupt_path, SH_INTEVT_IRL13); |
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INTERRUPT_CONNECT(tmpstr, d->irq_13); |
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snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]", |
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devinit->interrupt_path, SH_INTEVT_IRL11); |
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INTERRUPT_CONNECT(tmpstr, d->irq_11); |
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snprintf(tmpstr, sizeof(tmpstr), "%s.irq[0x%x]", |
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devinit->interrupt_path, SH_INTEVT_IRL9); |
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INTERRUPT_CONNECT(tmpstr, d->irq_9); |
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|
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memory_device_register(machine->memory, devinit->name, SYSASIC_BASE, |
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SYSASIC_SIZE, dev_dreamcast_asic_access, d, DM_DEFAULT, NULL); |
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|
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machine_add_tickfunction(devinit->machine, dev_dreamcast_asic_tick, d, |
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DREAMCAST_ASIC_TICK_SHIFT); |
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|
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return 1; |
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} |
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