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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: memory_mips_v2p.c,v 1.16 2007/04/28 01:46:07 debug Exp $ |
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*/ |
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|
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|
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/* |
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* translate_v2p(): |
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* |
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* Translate a virtual MIPS address to a physical address, by looking up the |
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* address in the TLB. On failure, an exception is generated (except for the |
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* case when FLAG_NOEXCEPTIONS is used). |
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* |
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* Note: This function is long and hairy, it is included several times with |
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* various defines set, to produce more or less optimized versions of |
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* the function for different emulated CPU types. |
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* |
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* V2P_MMU3K Defined for R2000/R3000 emulation. If it is not defined, |
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* R4000+/MIPS32/MIPS64 is presumed. |
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* V2P_MMU10K This enables the use of 44 userspace bits, instead of 40. |
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* V2P_MMU4100 VR41xx processors support 1 KB pages, so their page mask |
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* is slightly different. (The emulator only supports 4 KB |
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* pages, though.) |
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* V2P_MMU8K Not yet. (TODO.) |
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* |
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* |
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* Note: Unfortunately, the variable name vpn2 is poorly choosen for R2K/R3K, |
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* since it actual contains the vpn. |
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* |
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* Return values: |
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* 0 Failure |
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* 1 Success, the page is readable only |
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* 2 Success, the page is read/write |
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*/ |
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int TRANSLATE_ADDRESS(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_paddr, int flags) |
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{ |
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int writeflag = flags & FLAG_WRITEFLAG? MEM_WRITE : MEM_READ; |
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int no_exceptions = flags & FLAG_NOEXCEPTIONS; |
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int ksu, use_tlb, status, i; |
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uint64_t vaddr_vpn2=0, vaddr_asid=0; |
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int exccode, tlb_refill; |
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struct mips_coproc *cp0; |
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|
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#ifdef V2P_MMU3K |
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const int x_64 = 0; |
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const int n_tlbs = 64; |
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const int pmask = 0xfff; |
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uint64_t xuseg_top; /* Well, useg actually. */ |
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#else |
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#ifdef V2P_MMU10K |
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const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK_R10K; |
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uint64_t xuseg_top = ENTRYHI_VPN2_MASK_R10K | 0x1fffULL; |
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#else |
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#ifdef V2P_MMU4100 |
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const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK | 0x1800; |
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#else |
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const uint64_t vpn2_mask = ENTRYHI_R_MASK | ENTRYHI_VPN2_MASK; |
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#endif |
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uint64_t xuseg_top = ENTRYHI_VPN2_MASK | 0x1fffULL; |
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#endif |
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int x_64; /* non-zero for 64-bit address space accesses */ |
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int pageshift, n_tlbs; |
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int pmask; |
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#ifdef V2P_MMU4100 |
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const int pagemask_mask = PAGEMASK_MASK_R4100; |
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const int pagemask_shift = PAGEMASK_SHIFT_R4100; |
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const int pfn_shift = 10; |
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#else |
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const int pagemask_mask = PAGEMASK_MASK; |
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const int pagemask_shift = PAGEMASK_SHIFT; |
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const int pfn_shift = 12; |
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#endif |
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#endif /* !V2P_MMU3K */ |
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|
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|
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exccode = -1; |
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tlb_refill = 1; |
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|
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/* Cached values: */ |
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cp0 = cpu->cd.mips.coproc[0]; |
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status = cp0->reg[COP0_STATUS]; |
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|
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/* |
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* MIPS R4000+ and MIPS64 Address Translation: |
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* |
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* An address may be in one of the kernel segments, that are directly |
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* mapped to physical addresses, or the address needs to be looked up |
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* in the TLB entries. |
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* |
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* KSU: EXL: ERL: X: Name: Range: |
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* ---- ---- ---- -- ----- ------ |
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* |
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* 10 0 0 0 useg 0 - 0x7fffffff (2GB) (via TLB) |
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* 10 0 0 1 xuseg 0 - 0xffffffffff (1TB) (via TLB) |
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* |
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* 01 0 0 0 suseg 0 - 0x7fffffff (2GB via TLB) |
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* 01 0 0 0 ssseg 0xc0000000 - 0xdfffffff (0.5 GB via TLB) |
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* 01 0 0 1 xsuseg 0 - 0xffffffffff (1TB) (via TLB) |
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* 01 0 0 1 xsseg 0x4000000000000000 - 0x400000ffffffffff |
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* (1TB) (via TLB) |
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* 01 0 0 1 csseg 0xffffffffc0000000 - 0xffffffffdfffffff |
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* (0.5TB) (via TLB) |
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* |
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* 00 x x 0 kuseg 0 - 0x7fffffff (2GB) (via TLB) (*) |
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* 00 x x 0 kseg0 0x80000000 - 0x9fffffff (0.5GB) |
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* unmapped, cached |
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* 00 x x 0 kseg1 0xa0000000 - 0xbfffffff (0.5GB) |
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* unmapped, uncached |
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* 00 x x 0 ksseg 0xc0000000 - 0xdfffffff (0.5GB) (via TLB) |
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* 00 x x 0 kseg3 0xe0000000 - 0xffffffff (0.5GB) (via TLB) |
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* 00 x x 1 xksuseg 0 - 0xffffffffff (1TB) (via TLB) (*) |
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* 00 x x 1 xksseg 0x4000000000000000 - 0x400000ffffffffff |
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* (1TB) (via TLB) |
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* 00 x x 1 xkphys 0x8000000000000000 - 0xbfffffffffffffff |
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* 00 x x 1 xkseg 0xc000000000000000 - 0xc00000ff7fffffff |
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* 00 x x 1 ckseg0 0xffffffff80000000 - 0xffffffff9fffffff |
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* 00 x x 1 ckseg1 0xffffffffa0000000 - 0xffffffffbfffffff |
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* 00 x x 1 cksseg 0xffffffffc0000000 - 0xffffffffdfffffff |
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* 00 x x 1 ckseg3 0xffffffffe0000000 - 0xffffffffffffffff |
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* like 0x80000000 - 0xffffffff |
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* |
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* (*) = if ERL=1 then kuseg is not via TLB, but unmapped, |
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* uncached physical memory. |
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* |
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* (KSU==0 or EXL=1 or ERL=1 is enough to use k*seg*.) |
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* |
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* An invalid address causes an Address Error. |
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* |
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* See chapter 4, page 96, in the R4000 manual for more info! |
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*/ |
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|
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#ifdef V2P_MMU3K |
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if (status & MIPS1_SR_KU_CUR) |
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ksu = KSU_USER; |
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else |
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ksu = KSU_KERNEL; |
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|
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/* These are needed later: */ |
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vaddr_asid = cp0->reg[COP0_ENTRYHI] & R2K3K_ENTRYHI_ASID_MASK; |
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vaddr_vpn2 = vaddr & R2K3K_ENTRYHI_VPN_MASK; |
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#else |
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/* kx,sx,ux = 0 for 32-bit addressing, 1 for 64-bit addressing. */ |
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ksu = (status & STATUS_KSU_MASK) >> STATUS_KSU_SHIFT; |
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if (status & (STATUS_EXL | STATUS_ERL)) |
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ksu = KSU_KERNEL; |
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|
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switch (ksu) { |
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case KSU_USER: |
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x_64 = status & STATUS_UX; |
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break; |
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case KSU_KERNEL: |
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x_64 = status & STATUS_KX; |
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break; |
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case KSU_SUPERVISOR: |
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x_64 = status & STATUS_SX; |
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/* FALLTHROUGH, since supervisor address spaces are not |
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really implemented yet. */ |
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default:fatal("memory_mips_v2p.c: ksu=%i not yet implemented yet\n", |
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ksu); |
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exit(1); |
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} |
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|
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n_tlbs = cpu->cd.mips.cpu_type.nr_of_tlb_entries; |
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|
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/* Having this here suppresses a compiler warning: */ |
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pageshift = 12; |
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|
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/* KUSEG: 0x00000000 - 0x7fffffff if ERL = 1 and KSU = kernel: */ |
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if (ksu == KSU_KERNEL && (status & STATUS_ERL) && |
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vaddr <= 0x7fffffff) { |
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*return_paddr = vaddr & 0x7fffffff; |
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return 2; |
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} |
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|
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/* |
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* XKPHYS: 0x8000000000000000 - 0xbfffffffffffffff |
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* |
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* TODO: Is the correct error generated if accessing XKPHYS from |
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* usermode? |
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* |
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* TODO: Magic on SGI machines... Cache control, NUMA, etc.: |
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* 0x9000000080000000 = disable L2 cache (?) |
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* 0x90000000a0000000 = something on IP30? |
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* 0x92.... and 0x96... = NUMA on IP27 |
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*/ |
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if (ksu == KSU_KERNEL && (vaddr & ENTRYHI_R_MASK) == ENTRYHI_R_XKPHYS) { |
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*return_paddr = vaddr & (((uint64_t)1 << 44) - 1); |
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return 2; |
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} |
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|
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/* This is needed later: */ |
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vaddr_asid = cp0->reg[COP0_ENTRYHI] & ENTRYHI_ASID; |
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/* vpn2 depends on pagemask, which is not fixed on R4000 */ |
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#endif |
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|
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/* If 32-bit, truncate address and sign extend: */ |
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if (x_64 == 0) { |
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vaddr = (int32_t) vaddr; |
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xuseg_top = 0x7fffffff; |
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/* (Actually useg for R2000/R3000) */ |
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} |
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|
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if (vaddr <= xuseg_top) { |
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use_tlb = 1; |
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} else { |
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if (ksu == KSU_KERNEL) { |
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/* kseg0, kseg1: */ |
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if (vaddr >= (uint64_t)0xffffffff80000000ULL && |
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vaddr <= (uint64_t)0xffffffffbfffffffULL) { |
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*return_paddr = vaddr & 0x1fffffff; |
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return 2; |
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} |
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|
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/* other segments: */ |
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use_tlb = 1; |
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} else { |
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use_tlb = 0; |
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} |
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} |
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|
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if (use_tlb) { |
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#ifndef V2P_MMU3K |
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int odd = 0; |
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uint64_t cached_lo1 = 0; |
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#endif |
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int g_bit, v_bit, d_bit; |
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uint64_t cached_hi, cached_lo0; |
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uint64_t entry_vpn2 = 0, entry_asid, pfn; |
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int i_end; |
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|
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i = cpu->cd.mips.last_written_tlb_index; |
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i_end = i == 0? n_tlbs-1 : i - 1; |
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|
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/* Scan all TLB entries: */ |
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for (;;) { |
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#ifdef V2P_MMU3K |
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/* R3000 or similar: */ |
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cached_hi = cp0->tlbs[i].hi; |
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cached_lo0 = cp0->tlbs[i].lo0; |
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|
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entry_vpn2 = cached_hi & R2K3K_ENTRYHI_VPN_MASK; |
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entry_asid = cached_hi & R2K3K_ENTRYHI_ASID_MASK; |
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g_bit = cached_lo0 & R2K3K_ENTRYLO_G; |
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v_bit = cached_lo0 & R2K3K_ENTRYLO_V; |
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d_bit = cached_lo0 & R2K3K_ENTRYLO_D; |
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#else |
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/* R4000 or similar: */ |
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pmask = cp0->tlbs[i].mask & pagemask_mask; |
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cached_hi = cp0->tlbs[i].hi; |
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cached_lo0 = cp0->tlbs[i].lo0; |
| 277 |
cached_lo1 = cp0->tlbs[i].lo1; |
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|
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/* Optimized for minimum page size: */ |
| 280 |
if (pmask == 0) { |
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pageshift = pagemask_shift - 1; |
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entry_vpn2 = (cached_hi & vpn2_mask) |
| 283 |
>> pagemask_shift; |
| 284 |
vaddr_vpn2 = (vaddr & vpn2_mask) |
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>> pagemask_shift; |
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pmask = (1 << (pagemask_shift-1)) - 1; |
| 287 |
odd = (vaddr >> (pagemask_shift-1)) & 1; |
| 288 |
} else { |
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/* Non-standard page mask: */ |
| 290 |
switch (pmask | ((1 << pagemask_shift) - 1)) { |
| 291 |
case 0x00007ff: pageshift = 10; break; |
| 292 |
case 0x0001fff: pageshift = 12; break; |
| 293 |
case 0x0007fff: pageshift = 14; break; |
| 294 |
case 0x001ffff: pageshift = 16; break; |
| 295 |
case 0x007ffff: pageshift = 18; break; |
| 296 |
case 0x01fffff: pageshift = 20; break; |
| 297 |
case 0x07fffff: pageshift = 22; break; |
| 298 |
case 0x1ffffff: pageshift = 24; break; |
| 299 |
case 0x7ffffff: pageshift = 26; break; |
| 300 |
default:fatal("pmask=%08x\n", pmask); |
| 301 |
exit(1); |
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} |
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|
| 304 |
entry_vpn2 = (cached_hi & |
| 305 |
vpn2_mask) >> (pageshift + 1); |
| 306 |
vaddr_vpn2 = (vaddr & vpn2_mask) >> |
| 307 |
(pageshift + 1); |
| 308 |
pmask = (1 << pageshift) - 1; |
| 309 |
odd = (vaddr >> pageshift) & 1; |
| 310 |
} |
| 311 |
|
| 312 |
/* Assume even virtual page... */ |
| 313 |
v_bit = cached_lo0 & ENTRYLO_V; |
| 314 |
d_bit = cached_lo0 & ENTRYLO_D; |
| 315 |
|
| 316 |
#ifdef V2P_MMU8K |
| 317 |
/* |
| 318 |
* TODO: I don't really know anything about the R8000. |
| 319 |
* http://futuretech.mirror.vuurwerk.net/i2sec7.html |
| 320 |
* says that it has a three-way associative TLB with |
| 321 |
* 384 entries, 16KB page size, and some other things. |
| 322 |
* |
| 323 |
* It feels like things like the valid bit (ala R4000) |
| 324 |
* and dirty bit are not implemented the same on R8000. |
| 325 |
* |
| 326 |
* http://sgistuff.tastensuppe.de/documents/ |
| 327 |
* R8000_chipset.html |
| 328 |
* also has some info, but no details. |
| 329 |
*/ |
| 330 |
v_bit = 1; /* Big TODO */ |
| 331 |
d_bit = 1; |
| 332 |
#endif |
| 333 |
|
| 334 |
entry_asid = cached_hi & ENTRYHI_ASID; |
| 335 |
|
| 336 |
/* ... reload pfn, v_bit, d_bit if |
| 337 |
it was the odd virtual page: */ |
| 338 |
if (odd) { |
| 339 |
v_bit = cached_lo1 & ENTRYLO_V; |
| 340 |
d_bit = cached_lo1 & ENTRYLO_D; |
| 341 |
} |
| 342 |
#ifdef V2P_MMU4100 |
| 343 |
g_bit = cached_lo1 & cached_lo0 & ENTRYLO_G; |
| 344 |
#else |
| 345 |
g_bit = cached_hi & TLB_G; |
| 346 |
#endif |
| 347 |
|
| 348 |
#endif |
| 349 |
|
| 350 |
/* Is there a VPN and ASID match? */ |
| 351 |
if (entry_vpn2 == vaddr_vpn2 && |
| 352 |
(entry_asid == vaddr_asid || g_bit)) { |
| 353 |
/* debug("OK MAP 1, i=%i { vaddr=%016"PRIx64" " |
| 354 |
"==> paddr %016"PRIx64" v=%i d=%i " |
| 355 |
"asid=0x%02x }\n", i, (uint64_t) vaddr, |
| 356 |
(uint64_t) *return_paddr, v_bit?1:0, |
| 357 |
d_bit?1:0, vaddr_asid); */ |
| 358 |
if (v_bit) { |
| 359 |
if (d_bit || (!d_bit && |
| 360 |
writeflag == MEM_READ)) { |
| 361 |
uint64_t paddr; |
| 362 |
/* debug("OK MAP 2!!! { w=%i " |
| 363 |
"vaddr=%016"PRIx64" ==> " |
| 364 |
"d=%i v=%i paddr %016" |
| 365 |
PRIx64" ", |
| 366 |
writeflag, (uint64_t)vaddr, |
| 367 |
d_bit?1:0, v_bit?1:0, |
| 368 |
(uint64_t) *return_paddr); |
| 369 |
debug(", tlb entry %2i: ma" |
| 370 |
"sk=%016"PRIx64" hi=%016" |
| 371 |
PRIx64" lo0=%016"PRIx64 |
| 372 |
" lo1=%016"PRIx64"\n", |
| 373 |
i, cp0->tlbs[i].mask, cp0-> |
| 374 |
tlbs[i].hi, cp0->tlbs[i]. |
| 375 |
lo0, cp0->tlbs[i].lo1); |
| 376 |
*/ |
| 377 |
#ifdef V2P_MMU3K |
| 378 |
pfn = cached_lo0 & |
| 379 |
R2K3K_ENTRYLO_PFN_MASK; |
| 380 |
paddr = pfn | (vaddr & pmask); |
| 381 |
#else |
| 382 |
pfn = ((odd? cached_lo1 : |
| 383 |
cached_lo0) |
| 384 |
& ENTRYLO_PFN_MASK) |
| 385 |
>> ENTRYLO_PFN_SHIFT; |
| 386 |
paddr = ((pfn << pfn_shift) & |
| 387 |
~pmask) | (vaddr & pmask); |
| 388 |
#endif |
| 389 |
|
| 390 |
*return_paddr = paddr; |
| 391 |
return d_bit? 2 : 1; |
| 392 |
} else { |
| 393 |
/* TLB modif. exception */ |
| 394 |
tlb_refill = 0; |
| 395 |
exccode = EXCEPTION_MOD; |
| 396 |
goto exception; |
| 397 |
} |
| 398 |
} else { |
| 399 |
/* TLB invalid exception */ |
| 400 |
tlb_refill = 0; |
| 401 |
goto exception; |
| 402 |
} |
| 403 |
} |
| 404 |
|
| 405 |
if (i == i_end) |
| 406 |
break; |
| 407 |
|
| 408 |
/* Go to the next TLB entry: */ |
| 409 |
i ++; |
| 410 |
if (i == n_tlbs) |
| 411 |
i = 0; |
| 412 |
} |
| 413 |
} |
| 414 |
|
| 415 |
/* |
| 416 |
* We are here if for example userland code tried to access |
| 417 |
* kernel memory, OR if there was a TLB refill. |
| 418 |
*/ |
| 419 |
|
| 420 |
if (!use_tlb) { |
| 421 |
tlb_refill = 0; |
| 422 |
if (writeflag == MEM_WRITE) |
| 423 |
exccode = EXCEPTION_ADES; |
| 424 |
else |
| 425 |
exccode = EXCEPTION_ADEL; |
| 426 |
} |
| 427 |
|
| 428 |
exception: |
| 429 |
if (no_exceptions) |
| 430 |
return 0; |
| 431 |
|
| 432 |
/* TLB Load or Store exception: */ |
| 433 |
if (exccode == -1) { |
| 434 |
if (writeflag == MEM_WRITE) |
| 435 |
exccode = EXCEPTION_TLBS; |
| 436 |
else |
| 437 |
exccode = EXCEPTION_TLBL; |
| 438 |
} |
| 439 |
|
| 440 |
#ifdef V2P_MMU3K |
| 441 |
vaddr_asid >>= R2K3K_ENTRYHI_ASID_SHIFT; |
| 442 |
vaddr_vpn2 >>= 12; |
| 443 |
#endif |
| 444 |
|
| 445 |
mips_cpu_exception(cpu, exccode, tlb_refill, vaddr, |
| 446 |
0, vaddr_vpn2, vaddr_asid, x_64); |
| 447 |
|
| 448 |
/* Return failure: */ |
| 449 |
return 0; |
| 450 |
} |
| 451 |
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