src/native/native_amd64.c

/*
 *  Copyright (C) 2007  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: native_amd64.c,v 1.2 2007/02/16 16:48:08 debug Exp $
 *
 *  Native code generation backend for AMD64 and i386.
 *
 *  TODO: This is just a dummy so far, there is no native code generation
 *        in GXemul.
 *
 *  TODO 2: This is not really for i386 (32-bit) yet.
 *
 *  HOST_ARCH_AMD64 is set for AMD64 hosts, and HOST_ARCH_I386 for i386 hosts.
 *
 *  Argument order:  edi, esi, edx, ecx, e8d, r9d, ...
 *  edi should always point to the cpu struct, esi to the ic.
 */

#define NATIVE_FUNCTION_ALIGNMENT               32

#define OUTPUT_32(v) {                                          \
        *p++ = (v) & 255; *p++ = ((v) >> 8) & 255;              \
        *p++ = ((v) >> 16) & 255; *p++ = ((v) >> 24) & 255; }
#define OUTPUT_64(v) {                                          \
        *p++ = (v) & 255; *p++ = ((v) >> 8) & 255;              \
        *p++ = ((v) >> 16) & 255; *p++ = ((v) >> 24) & 255;     \
        *p++ = ((v) >> 32) & 255; *p++ = ((v) >> 40) & 255;     \
        *p++ = ((v) >> 48) & 255; *p++ = ((v) >> 56) & 255; }
#ifdef HOST_ARCH_AMD64
#define OUTPUT_HOST_SIZE(v)     OUTPUT_64(v)
#else
#define OUTPUT_HOST_SIZE(v)     OUTPUT_32(v)
#endif

void native_output_function_prelude(struct cpu *cpu)
{
        printf("no\n");
        abort();
}

void native_output_next_ic_increment(struct cpu *cpu)
{
        uint8_t *p = cpu->native_cur_output_ptr;
        uint64_t y1 = (size_t) (void *) &cpu->n_translated_instrs;
        uint64_t y2 = (size_t) (void *) &cpu->cd.mips.next_ic;
        int inc = cpu->nr_of_instructions_translated_to_native - 1;

        printf("not yet\n");
        abort();

        *p++ = 0x48; *p++ = 0xb8;
        OUTPUT_HOST_SIZE(y1);           /*  rax = y1  */

        *p++ = 0x48; *p++ = 0xba;
        OUTPUT_HOST_SIZE(y2);           /*  rdx = y2  */

        *p++ = 0x81; *p++ = 0x00;       /*  add 32-bit word to (rax)  */
        OUTPUT_32(inc);

        inc *= 0x20;

        *p++ = 0x48; *p++ = 0x81; *p++ = 0x02;  /*  add 64-bit word to (rdx)  */
        OUTPUT_32(inc);

        cpu->native_cur_output_ptr = p;
}

void native_output_function_postlude(struct cpu *cpu)
{
        uint8_t *p = cpu->native_cur_output_ptr;
        *p++ = 0xc3;    /*  ret, or retq  */
        cpu->native_cur_output_ptr = p;
}

int native_nop(struct cpu *cpu)
{
        native_start(cpu);
        cpu->nr_of_instructions_translated_to_native ++;
        return 1;
}

int native_set_u32_p32(struct cpu *cpu, uint32_t v, uint32_t *p1)
{
        uint64_t y1 = (size_t) (void *) p1;
        uint8_t *p;

        native_start(cpu);

        p = cpu->native_cur_output_ptr;

        *p++ = 0xb8;            /*  set eax to value  */
        OUTPUT_32(v);

        *p++ = 0xa3;            /*  store eax into memory  */
        OUTPUT_HOST_SIZE(y1);

        cpu->nr_of_instructions_translated_to_native ++;
        cpu->native_cur_output_ptr = p;

        return 1;
}

1	/*
2	* Copyright (C) 2007 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: native_amd64.c,v 1.2 2007/02/16 16:48:08 debug Exp $
29	*
30	* Native code generation backend for AMD64 and i386.
31	*
32	* TODO: This is just a dummy so far, there is no native code generation
33	* in GXemul.
34	*
35	* TODO 2: This is not really for i386 (32-bit) yet.
36	*
37	* HOST_ARCH_AMD64 is set for AMD64 hosts, and HOST_ARCH_I386 for i386 hosts.
38	*
39	* Argument order: edi, esi, edx, ecx, e8d, r9d, ...
40	* edi should always point to the cpu struct, esi to the ic.
41	*/
42
43	#define NATIVE_FUNCTION_ALIGNMENT 32
44
45	#define OUTPUT_32(v) { \
46	p++ = (v) & 255; p++ = ((v) >> 8) & 255; \
47	p++ = ((v) >> 16) & 255; p++ = ((v) >> 24) & 255; }
48	#define OUTPUT_64(v) { \
49	p++ = (v) & 255; p++ = ((v) >> 8) & 255; \
50	p++ = ((v) >> 16) & 255; p++ = ((v) >> 24) & 255; \
51	p++ = ((v) >> 32) & 255; p++ = ((v) >> 40) & 255; \
52	p++ = ((v) >> 48) & 255; p++ = ((v) >> 56) & 255; }
53	#ifdef HOST_ARCH_AMD64
54	#define OUTPUT_HOST_SIZE(v) OUTPUT_64(v)
55	#else
56	#define OUTPUT_HOST_SIZE(v) OUTPUT_32(v)
57	#endif
58
59	void native_output_function_prelude(struct cpu *cpu)
60	{
61	printf("no\n");
62	abort();
63	}
64
65	void native_output_next_ic_increment(struct cpu *cpu)
66	{
67	uint8_t *p = cpu->native_cur_output_ptr;
68	uint64_t y1 = (size_t) (void *) &cpu->n_translated_instrs;
69	uint64_t y2 = (size_t) (void *) &cpu->cd.mips.next_ic;
70	int inc = cpu->nr_of_instructions_translated_to_native - 1;
71
72	printf("not yet\n");
73	abort();
74
75	p++ = 0x48; p++ = 0xb8;
76	OUTPUT_HOST_SIZE(y1); /* rax = y1 */
77
78	p++ = 0x48; p++ = 0xba;
79	OUTPUT_HOST_SIZE(y2); /* rdx = y2 */
80
81	p++ = 0x81; p++ = 0x00; /* add 32-bit word to (rax) */
82	OUTPUT_32(inc);
83
84	inc *= 0x20;
85
86	p++ = 0x48; p++ = 0x81; p++ = 0x02; / add 64-bit word to (rdx) */
87	OUTPUT_32(inc);
88
89	cpu->native_cur_output_ptr = p;
90	}
91
92	void native_output_function_postlude(struct cpu *cpu)
93	{
94	uint8_t *p = cpu->native_cur_output_ptr;
95	p++ = 0xc3; / ret, or retq */
96	cpu->native_cur_output_ptr = p;
97	}
98
99	int native_nop(struct cpu *cpu)
100	{
101	native_start(cpu);
102	cpu->nr_of_instructions_translated_to_native ++;
103	return 1;
104	}
105
106	int native_set_u32_p32(struct cpu cpu, uint32_t v, uint32_t p1)
107	{
108	uint64_t y1 = (size_t) (void *) p1;
109	uint8_t *p;
110
111	native_start(cpu);
112
113	p = cpu->native_cur_output_ptr;
114
115	p++ = 0xb8; / set eax to value */
116	OUTPUT_32(v);
117
118	p++ = 0xa3; / store eax into memory */
119	OUTPUT_HOST_SIZE(y1);
120
121	cpu->nr_of_instructions_translated_to_native ++;
122	cpu->native_cur_output_ptr = p;
123
124	return 1;
125	}
126