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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: memory_rw.c,v 1.101 2007/02/10 14:04:51 debug Exp $ |
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* |
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* Generic memory_rw(), with special hacks for specific CPU families. |
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* |
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* Example for inclusion from memory_mips.c: |
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* |
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* MEMORY_RW should be mips_memory_rw |
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* MEM_MIPS should be defined |
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*/ |
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|
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|
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/* |
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* memory_rw(): |
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* |
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* Read or write data from/to memory. |
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* |
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* cpu the cpu doing the read/write |
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* mem the memory object to use |
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* vaddr the virtual address |
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* data a pointer to the data to be written to memory, or |
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* a placeholder for data when reading from memory |
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* len the length of the 'data' buffer |
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* writeflag set to MEM_READ or MEM_WRITE |
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* misc_flags CACHE_{NONE,DATA,INSTRUCTION} | other flags |
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* |
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* If the address indicates access to a memory mapped device, that device' |
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* read/write access function is called. |
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* |
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* This function should not be called with cpu == NULL. |
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* |
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* Returns one of the following: |
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* MEMORY_ACCESS_FAILED |
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* MEMORY_ACCESS_OK |
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* |
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* (MEMORY_ACCESS_FAILED is 0.) |
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*/ |
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int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int misc_flags) |
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{ |
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#ifdef MEM_ALPHA |
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const int offset_mask = 0x1fff; |
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#else |
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const int offset_mask = 0xfff; |
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#endif |
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|
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#ifndef MEM_USERLAND |
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int ok = 1; |
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#endif |
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uint64_t paddr; |
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int cache, no_exceptions, offset; |
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unsigned char *memblock; |
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int dyntrans_device_danger = 0; |
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|
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no_exceptions = misc_flags & NO_EXCEPTIONS; |
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cache = misc_flags & CACHE_FLAGS_MASK; |
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|
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|
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#ifdef MEM_USERLAND |
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#ifdef MEM_ALPHA |
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paddr = vaddr; |
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#else |
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paddr = vaddr & 0x7fffffff; |
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#endif |
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#else /* !MEM_USERLAND */ |
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if (misc_flags & PHYSICAL || cpu->translate_v2p == NULL) { |
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paddr = vaddr; |
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} else { |
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ok = cpu->translate_v2p(cpu, vaddr, &paddr, |
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(writeflag? FLAG_WRITEFLAG : 0) + |
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(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
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#ifdef MEM_ARM |
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+ (misc_flags & MEMORY_USER_ACCESS) |
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#endif |
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+ (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0)); |
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|
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/* |
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* If the translation caused an exception, or was invalid in |
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* some way, then simply return without doing the memory |
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* access: |
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*/ |
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if (!ok) |
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return MEMORY_ACCESS_FAILED; |
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} |
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|
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#endif /* !MEM_USERLAND */ |
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|
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|
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#ifndef MEM_USERLAND |
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/* |
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* Memory mapped device? |
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* |
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* TODO: if paddr < base, but len enough, then the device should |
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* still be written to! |
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*/ |
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if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) { |
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uint64_t orig_paddr = paddr; |
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int i, start, end, res; |
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|
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#if 0 |
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|
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TODO: The correct solution for this is to add RAM devices _around_ the |
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dangerous device. The solution below incurs a slowdown for _everything_, |
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not just the device in question. |
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|
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/* |
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* Really really slow, but unfortunately necessary. This is |
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* to avoid the folowing scenario: |
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* |
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* a) offsets 0x000..0x123 are normal memory |
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* b) offsets 0x124..0x777 are a device |
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* |
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* 1) a read is done from offset 0x100. the page is |
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* added to the dyntrans system as a "RAM" page |
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* 2) a dyntranslated read is done from offset 0x200, |
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* which should access the device, but since the |
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* entire page is added, it will access non-existant |
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* RAM instead, without warning. |
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* |
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* Setting dyntrans_device_danger = 1 on accesses which are |
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* on _any_ offset on pages that are device mapped avoids |
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* this problem, but it is probably not very fast. |
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* |
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* TODO: Convert this into a quick (multi-level, 64-bit) |
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* address space lookup, to find dangerous pages. |
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*/ |
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for (i=0; i<mem->n_mmapped_devices; i++) |
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if (paddr >= (mem->devices[i].baseaddr & ~offset_mask)&& |
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paddr <= ((mem->devices[i].endaddr-1)|offset_mask)){ |
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dyntrans_device_danger = 1; |
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break; |
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} |
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#endif |
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|
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start = 0; end = mem->n_mmapped_devices - 1; |
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i = mem->last_accessed_device; |
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|
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/* Scan through all devices: */ |
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do { |
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if (paddr >= mem->devices[i].baseaddr && |
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paddr < mem->devices[i].endaddr) { |
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/* Found a device, let's access it: */ |
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mem->last_accessed_device = i; |
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|
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paddr -= mem->devices[i].baseaddr; |
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if (paddr + len > mem->devices[i].length) |
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len = mem->devices[i].length - paddr; |
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|
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if (cpu->update_translation_table != NULL && |
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!(ok & MEMORY_NOT_FULL_PAGE) && |
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mem->devices[i].flags & DM_DYNTRANS_OK) { |
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int wf = writeflag == MEM_WRITE? 1 : 0; |
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unsigned char *host_addr; |
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|
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if (!(mem->devices[i].flags & |
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DM_DYNTRANS_WRITE_OK)) |
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wf = 0; |
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|
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if (writeflag && wf) { |
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if (paddr < mem->devices[i]. |
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dyntrans_write_low) |
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mem->devices[i]. |
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dyntrans_write_low = |
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paddr &~offset_mask; |
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if (paddr >= mem->devices[i]. |
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dyntrans_write_high) |
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mem->devices[i]. |
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dyntrans_write_high = |
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paddr | offset_mask; |
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} |
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|
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if (mem->devices[i].flags & |
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DM_EMULATED_RAM) { |
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/* MEM_WRITE to force the page |
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to be allocated, if it |
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wasn't already */ |
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uint64_t *pp = (uint64_t *)mem-> |
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devices[i].dyntrans_data; |
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uint64_t p = orig_paddr - *pp; |
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host_addr = |
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memory_paddr_to_hostaddr( |
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mem, p & ~offset_mask, |
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MEM_WRITE); |
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} else { |
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host_addr = mem->devices[i]. |
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dyntrans_data + |
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(paddr & ~offset_mask); |
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} |
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|
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cpu->update_translation_table(cpu, |
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vaddr & ~offset_mask, host_addr, |
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wf, orig_paddr & ~offset_mask); |
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} |
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|
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res = 0; |
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if (!no_exceptions || (mem->devices[i].flags & |
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DM_READS_HAVE_NO_SIDE_EFFECTS)) |
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res = mem->devices[i].f(cpu, mem, paddr, |
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data, len, writeflag, |
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mem->devices[i].extra); |
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|
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if (res == 0) |
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res = -1; |
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|
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/* |
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* If accessing the memory mapped device |
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* failed, then return with a DBE exception. |
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*/ |
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if (res <= 0 && !no_exceptions) { |
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debug("%s device '%s' addr %08lx " |
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"failed\n", writeflag? |
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"writing to" : "reading from", |
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mem->devices[i].name, (long)paddr); |
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#ifdef MEM_MIPS |
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mips_cpu_exception(cpu, EXCEPTION_DBE, |
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0, vaddr, 0, 0, 0, 0); |
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#endif |
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return MEMORY_ACCESS_FAILED; |
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} |
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goto do_return_ok; |
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} |
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|
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if (paddr < mem->devices[i].baseaddr) |
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end = i - 1; |
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if (paddr >= mem->devices[i].endaddr) |
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start = i + 1; |
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i = (start + end) >> 1; |
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} while (start <= end); |
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} |
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|
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|
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#ifdef MEM_MIPS |
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/* |
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* Data and instruction cache emulation: |
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*/ |
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|
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switch (cpu->cd.mips.cpu_type.mmu_model) { |
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case MMU3K: |
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/* if not uncached addess (TODO: generalize this) */ |
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if (!(misc_flags & PHYSICAL) && cache != CACHE_NONE && |
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!((vaddr & 0xffffffffULL) >= 0xa0000000ULL && |
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(vaddr & 0xffffffffULL) <= 0xbfffffffULL)) { |
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if (memory_cache_R3000(cpu, cache, paddr, |
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writeflag, len, data)) |
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goto do_return_ok; |
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} |
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break; |
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default: |
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/* R4000 etc */ |
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/* TODO */ |
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; |
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} |
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#endif /* MEM_MIPS */ |
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|
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|
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/* Outside of physical RAM? */ |
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if (paddr >= mem->physical_max) { |
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#ifdef MEM_MIPS |
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if ((paddr & 0xffffc00000ULL) == 0x1fc00000) { |
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/* Ok, this is PROM stuff */ |
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} else if ((paddr & 0xfffff00000ULL) == 0x1ff00000) { |
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/* Sprite reads from this area of memory... */ |
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/* TODO: is this still correct? */ |
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if (writeflag == MEM_READ) |
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memset(data, 0, len); |
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goto do_return_ok; |
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} else |
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#endif /* MIPS */ |
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{ |
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if (paddr >= mem->physical_max && !no_exceptions) |
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memory_warn_about_unimplemented_addr |
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(cpu, mem, writeflag, paddr, data, len); |
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|
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if (writeflag == MEM_READ) { |
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/* Return all zeroes? (Or 0xff? TODO) */ |
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memset(data, 0, len); |
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|
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#ifdef MEM_MIPS |
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/* |
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* For real data/instruction accesses, cause |
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* an exceptions on an illegal read: |
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*/ |
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if (cache != CACHE_NONE && cpu->machine-> |
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dbe_on_nonexistant_memaccess && |
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!no_exceptions) { |
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if (paddr >= mem->physical_max && |
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paddr < mem->physical_max+1048576) |
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mips_cpu_exception(cpu, |
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EXCEPTION_DBE, 0, vaddr, 0, |
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0, 0, 0); |
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} |
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#endif /* MEM_MIPS */ |
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} |
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|
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/* Hm? Shouldn't there be a DBE exception for |
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invalid writes as well? TODO */ |
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|
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goto do_return_ok; |
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} |
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} |
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|
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#endif /* ifndef MEM_USERLAND */ |
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|
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|
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/* |
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* Uncached access: |
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* |
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* 1) Translate the physical address to a host address. |
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* |
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* 2) Insert this virtual->physical->host translation into the |
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* fast translation arrays (using update_translation_table()). |
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* |
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* 3) If this was a Write, then invalidate any code translations |
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* in that page. |
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*/ |
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memblock = memory_paddr_to_hostaddr(mem, paddr & ~offset_mask, |
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writeflag); |
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if (memblock == NULL) { |
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if (writeflag == MEM_READ) |
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memset(data, 0, len); |
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goto do_return_ok; |
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} |
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|
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offset = paddr & offset_mask; |
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|
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if (cpu->update_translation_table != NULL && !dyntrans_device_danger |
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#ifdef MEM_MIPS |
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/* Ugly hack for R2000/R3000 caches: */ |
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&& (cpu->cd.mips.cpu_type.mmu_model != MMU3K || |
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!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES)) |
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#endif |
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#ifndef MEM_MIPS |
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/* && !(misc_flags & MEMORY_USER_ACCESS) */ |
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#ifndef MEM_USERLAND |
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&& !(ok & MEMORY_NOT_FULL_PAGE) |
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#endif |
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#endif |
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&& !no_exceptions) |
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cpu->update_translation_table(cpu, vaddr & ~offset_mask, |
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memblock, (misc_flags & MEMORY_USER_ACCESS) | |
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#if !defined(MEM_MIPS) && !defined(MEM_USERLAND) |
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(cache == CACHE_INSTRUCTION? |
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(writeflag == MEM_WRITE? 1 : 0) : ok - 1), |
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#else |
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(writeflag == MEM_WRITE? 1 : 0), |
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#endif |
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paddr & ~offset_mask); |
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|
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/* |
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* If writing, then invalidate code translations for the (physical) |
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* page address: |
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*/ |
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if (writeflag == MEM_WRITE && cpu->invalidate_code_translation != NULL) |
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cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR); |
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|
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if ((paddr&((1<<BITS_PER_MEMBLOCK)-1)) + len > (1<<BITS_PER_MEMBLOCK)) { |
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printf("Write over memblock boundary?\n"); |
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exit(1); |
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} |
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|
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if (writeflag == MEM_WRITE) { |
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/* Ugly optimization, but it works: */ |
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if (len == sizeof(uint32_t) && (offset & 3)==0 |
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&& ((size_t)data&3)==0) |
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*(uint32_t *)(memblock + offset) = *(uint32_t *)data; |
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else if (len == sizeof(uint8_t)) |
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*(uint8_t *)(memblock + offset) = *(uint8_t *)data; |
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else |
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memcpy(memblock + offset, data, len); |
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} else { |
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/* Ugly optimization, but it works: */ |
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if (len == sizeof(uint32_t) && (offset & 3)==0 |
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&& ((size_t)data&3)==0) |
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*(uint32_t *)data = *(uint32_t *)(memblock + offset); |
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else if (len == sizeof(uint8_t)) |
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*(uint8_t *)data = *(uint8_t *)(memblock + offset); |
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else |
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memcpy(data, memblock + offset, len); |
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} |
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|
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|
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do_return_ok: |
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return MEMORY_ACCESS_OK; |
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} |
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