| 1 |
/* gxemul: $Id: wdcreg.h,v 1.3 2005/09/10 22:18:57 debug Exp $ */ |
| 2 |
/* $NetBSD: wdcreg.h,v 1.25 2002/03/31 19:47:39 bouyer Exp $ */ |
| 3 |
|
| 4 |
#ifndef WDCREG_H |
| 5 |
#define WDCREG_H |
| 6 |
|
| 7 |
/*- |
| 8 |
* Copyright (c) 1991 The Regents of the University of California. |
| 9 |
* All rights reserved. |
| 10 |
* |
| 11 |
* This code is derived from software contributed to Berkeley by |
| 12 |
* William Jolitz. |
| 13 |
* |
| 14 |
* Redistribution and use in source and binary forms, with or without |
| 15 |
* modification, are permitted provided that the following conditions |
| 16 |
* are met: |
| 17 |
* 1. Redistributions of source code must retain the above copyright |
| 18 |
* notice, this list of conditions and the following disclaimer. |
| 19 |
* 2. Redistributions in binary form must reproduce the above copyright |
| 20 |
* notice, this list of conditions and the following disclaimer in the |
| 21 |
* documentation and/or other materials provided with the distribution. |
| 22 |
* 3. All advertising materials mentioning features or use of this software |
| 23 |
* must display the following acknowledgement: |
| 24 |
* This product includes software developed by the University of |
| 25 |
* California, Berkeley and its contributors. |
| 26 |
* 4. Neither the name of the University nor the names of its contributors |
| 27 |
* may be used to endorse or promote products derived from this software |
| 28 |
* without specific prior written permission. |
| 29 |
* |
| 30 |
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 31 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 32 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 33 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 34 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 35 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 36 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 37 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 38 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 39 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 40 |
* SUCH DAMAGE. |
| 41 |
* |
| 42 |
* @(#)wdreg.h 7.1 (Berkeley) 5/9/91 |
| 43 |
*/ |
| 44 |
|
| 45 |
/* |
| 46 |
* Disk Controller register definitions. |
| 47 |
*/ |
| 48 |
|
| 49 |
/* offsets of registers in the 'regular' register region */ |
| 50 |
#define wd_data 0 /* data register (R/W - 16 bits) */ |
| 51 |
#define wd_error 1 /* error register (R) */ |
| 52 |
#define wd_precomp 1 /* write precompensation (W) */ |
| 53 |
#define wd_features 1 /* features (W), same as wd_precomp */ |
| 54 |
#define wd_seccnt 2 /* sector count (R/W) */ |
| 55 |
#define wd_ireason 2 /* interrupt reason (R/W) (for atapi) */ |
| 56 |
#define wd_sector 3 /* first sector number (R/W) */ |
| 57 |
#define wd_cyl_lo 4 /* cylinder address, low byte (R/W) */ |
| 58 |
#define wd_cyl_hi 5 /* cylinder address, high byte (R/W) */ |
| 59 |
#define wd_sdh 6 /* sector size/drive/head (R/W) */ |
| 60 |
#define wd_command 7 /* command register (W) */ |
| 61 |
#define wd_status 7 /* immediate status (R) */ |
| 62 |
#define wd_lba_lo 3 /* lba address, low byte (RW) */ |
| 63 |
#define wd_lba_mi 4 /* lba address, middle byte (RW) */ |
| 64 |
#define wd_lba_hi 5 /* lba address, high byte (RW) */ |
| 65 |
|
| 66 |
/* offsets of registers in the auxiliary register region */ |
| 67 |
#define wd_aux_altsts 0 /* alternate fixed disk status (R) */ |
| 68 |
#define wd_aux_ctlr 0 /* fixed disk controller control (W) */ |
| 69 |
#define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */ |
| 70 |
#define WDCTL_RST 0x04 /* reset the controller */ |
| 71 |
#define WDCTL_IDS 0x02 /* disable controller interrupts */ |
| 72 |
#if 0 /* NOT MAPPED; fd uses this register on PCs */ |
| 73 |
#define wd_digin 1 /* disk controller input (R) */ |
| 74 |
#endif |
| 75 |
|
| 76 |
/* |
| 77 |
* Status bits. |
| 78 |
*/ |
| 79 |
#define WDCS_BSY 0x80 /* busy */ |
| 80 |
#define WDCS_DRDY 0x40 /* drive ready */ |
| 81 |
#define WDCS_DWF 0x20 /* drive write fault */ |
| 82 |
#define WDCS_DSC 0x10 /* drive seek complete */ |
| 83 |
#define WDCS_DRQ 0x08 /* data request */ |
| 84 |
#define WDCS_CORR 0x04 /* corrected data */ |
| 85 |
#define WDCS_IDX 0x02 /* index */ |
| 86 |
#define WDCS_ERR 0x01 /* error */ |
| 87 |
#define WDCS_BITS \ |
| 88 |
"\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err" |
| 89 |
|
| 90 |
/* |
| 91 |
* Error bits. |
| 92 |
*/ |
| 93 |
#define WDCE_BBK 0x80 /* bad block detected */ |
| 94 |
#define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ |
| 95 |
#define WDCE_UNC 0x40 /* uncorrectable data error */ |
| 96 |
#define WDCE_MC 0x20 /* media changed */ |
| 97 |
#define WDCE_IDNF 0x10 /* id not found */ |
| 98 |
#define WDCE_MCR 0x08 /* media change requested */ |
| 99 |
#define WDCE_ABRT 0x04 /* aborted command */ |
| 100 |
#define WDCE_TK0NF 0x02 /* track 0 not found */ |
| 101 |
#define WDCE_AMNF 0x01 /* address mark not found */ |
| 102 |
|
| 103 |
/* |
| 104 |
* Commands for Disk Controller. |
| 105 |
*/ |
| 106 |
#define WDCC_NOP 0x00 /* Always fail with "aborted command" */ |
| 107 |
#define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ |
| 108 |
|
| 109 |
#define WDCC_READ 0x20 /* disk read code */ |
| 110 |
#define WDCC_WRITE 0x30 /* disk write code */ |
| 111 |
#define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ |
| 112 |
#define WDCC__NORETRY 0x01 /* modifier -- no retrys */ |
| 113 |
|
| 114 |
#define WDCC_FORMAT 0x50 /* disk format code */ |
| 115 |
#define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ |
| 116 |
#define WDCC_IDP 0x91 /* initialize drive parameters */ |
| 117 |
|
| 118 |
#define WDCC_SMART 0xb0 /* Self Mon, Analysis, Reporting Tech */ |
| 119 |
|
| 120 |
#define WDCC_READMULTI 0xc4 /* read multiple */ |
| 121 |
#define WDCC_WRITEMULTI 0xc5 /* write multiple */ |
| 122 |
#define WDCC_SETMULTI 0xc6 /* set multiple mode */ |
| 123 |
|
| 124 |
#define WDCC_READDMA 0xc8 /* read with DMA */ |
| 125 |
#define WDCC_WRITEDMA 0xca /* write with DMA */ |
| 126 |
|
| 127 |
#define WDCC_ACKMC 0xdb /* acknowledge media change */ |
| 128 |
#define WDCC_LOCK 0xde /* lock drawer */ |
| 129 |
#define WDCC_UNLOCK 0xdf /* unlock drawer */ |
| 130 |
|
| 131 |
#define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ |
| 132 |
#define WDCC_IDENTIFY 0xec /* read parameters from controller */ |
| 133 |
#define SET_FEATURES 0xef /* set features */ |
| 134 |
|
| 135 |
#define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ |
| 136 |
#define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ |
| 137 |
#define WDCC_SLEEP 0xe6 /* enter sleep mode */ |
| 138 |
#define WDCC_STANDBY 0xe2 /* set standby timer & enter standby */ |
| 139 |
#define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ |
| 140 |
#define WDCC_CHECK_PWR 0xe5 /* check power mode */ |
| 141 |
|
| 142 |
#define WDCC_SEC_SET_PASSWORD 0xf1 /* set user or master password */ |
| 143 |
#define WDCC_SEC_UNLOCK 0xf2 /* authenticate */ |
| 144 |
#define WDCC_SEC_ERASE_PREPARE 0xf3 /* enable device erasing */ |
| 145 |
#define WDCC_SEC_ERASE_UNIT 0xf4 /* erase all user data */ |
| 146 |
#define WDCC_SEC_FREEZE_LOCK 0xf5 /* prevent password changes */ |
| 147 |
#define WDCC_SEC_DISABLE_PASSWORD 0xf6 /* disable lock mode */ |
| 148 |
|
| 149 |
|
| 150 |
/* |
| 151 |
* Big Drive support |
| 152 |
*/ |
| 153 |
#define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ |
| 154 |
#define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ |
| 155 |
|
| 156 |
#define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ |
| 157 |
#define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ |
| 158 |
|
| 159 |
#define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ |
| 160 |
#define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ |
| 161 |
|
| 162 |
/* Subcommands for SET_FEATURES (features register) */ |
| 163 |
#define WDSF_EN_WR_CACHE 0x02 |
| 164 |
#define WDSF_SET_MODE 0x03 |
| 165 |
#define WDSF_REASSIGN_EN 0x04 |
| 166 |
#define WDSF_RETRY_DS 0x33 |
| 167 |
#define WDSF_SET_CACHE_SGMT 0x54 |
| 168 |
#define WDSF_READAHEAD_DS 0x55 |
| 169 |
#define WDSF_POD_DS 0x66 |
| 170 |
#define WDSF_ECC_DS 0x77 |
| 171 |
#define WDSF_WRITE_CACHE_DS 0x82 |
| 172 |
#define WDSF_REASSIGN_DS 0x84 |
| 173 |
#define WDSF_ECC_EN 0x88 |
| 174 |
#define WDSF_RETRY_EN 0x99 |
| 175 |
#define WDSF_SET_CURRENT 0x9a |
| 176 |
#define WDSF_READAHEAD_EN 0xaa |
| 177 |
#define WDSF_PREFETCH_SET 0xab |
| 178 |
#define WDSF_POD_EN 0xcc |
| 179 |
|
| 180 |
/* Subcommands for SMART (features register) */ |
| 181 |
#define WDSM_RD_DATA 0xd0 |
| 182 |
#define WDSM_ATTR_AUTOSAVE_EN 0xd2 |
| 183 |
#define WDSM_SAVE_ATTR 0xd3 |
| 184 |
#define WDSM_EXEC_OFFL_IMM 0xd4 |
| 185 |
#define WDSM_ENABLE_OPS 0xd8 |
| 186 |
#define WDSM_DISABLE_OPS 0xd9 |
| 187 |
#define WDSM_STATUS 0xda |
| 188 |
|
| 189 |
#define WDSMART_CYL_LO 0x4f |
| 190 |
#define WDSMART_CYL_HI 0xc2 |
| 191 |
|
| 192 |
|
| 193 |
/* parameters uploaded to device/heads register */ |
| 194 |
#define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ |
| 195 |
#define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ |
| 196 |
#define WDSD_LBA 0x40 /* logical block addressing */ |
| 197 |
|
| 198 |
/* Commands for ATAPI devices */ |
| 199 |
#define ATAPI_CHECK_POWER_MODE 0xe5 |
| 200 |
#define ATAPI_EXEC_DRIVE_DIAGS 0x90 |
| 201 |
#define ATAPI_IDLE_IMMEDIATE 0xe1 |
| 202 |
#define ATAPI_NOP 0x00 |
| 203 |
#define ATAPI_PKT_CMD 0xa0 |
| 204 |
#define ATAPI_IDENTIFY_DEVICE 0xa1 |
| 205 |
#define ATAPI_SOFT_RESET 0x08 |
| 206 |
#define ATAPI_SLEEP 0xe6 |
| 207 |
#define ATAPI_STANDBY_IMMEDIATE 0xe0 |
| 208 |
|
| 209 |
/* Bytes used by ATAPI_PACKET_COMMAND ( feature register) */ |
| 210 |
#define ATAPI_PKT_CMD_FTRE_DMA 0x01 |
| 211 |
#define ATAPI_PKT_CMD_FTRE_OVL 0x02 |
| 212 |
|
| 213 |
/* ireason */ |
| 214 |
#define WDCI_CMD 0x01 /* command(1) or data(0) */ |
| 215 |
#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ |
| 216 |
#define WDCI_RELEASE 0x04 /* bus released until completion */ |
| 217 |
|
| 218 |
#define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) |
| 219 |
#define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) |
| 220 |
#define PHASE_DATAOUT (WDCS_DRQ) |
| 221 |
#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) |
| 222 |
#define PHASE_ABORTED (0) |
| 223 |
|
| 224 |
#endif /* WDCREG_H */ |
Parent Directory
| 
Revision Log