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/* gxemul: $Id: siireg.h,v 1.3 2005/03/05 12:34:03 debug Exp $ */ |
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/* $NetBSD: siireg.h,v 1.4 1994/10/26 21:09:22 cgd Exp $ */ |
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|
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/* |
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* Copyright (c) 1992, 1993 |
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* The Regents of the University of California. All rights reserved. |
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* |
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* This code is derived from software contributed to Berkeley by |
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* Ralph Campbell. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the University of |
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* California, Berkeley and its contributors. |
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* 4. Neither the name of the University nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* @(#)siireg.h 8.1 (Berkeley) 6/10/93 |
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* |
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* sii.h -- |
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* |
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* SII registers. |
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* |
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* Copyright (C) 1989 Digital Equipment Corporation. |
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* Permission to use, copy, modify, and distribute this software and |
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* its documentation for any purpose and without fee is hereby granted, |
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* provided that the above copyright notice appears in all copies. |
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* Digital Equipment Corporation makes no representations about the |
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* suitability of this software for any purpose. It is provided "as is" |
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* without express or implied warranty. |
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* |
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* from: Header: /sprite/src/kernel/dev/ds3100.md/RCS/sii.h, |
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* v 1.2 89/08/15 19:53:04 rab Exp SPRITE (DECWRL) |
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*/ |
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|
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#ifndef _SII |
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#define _SII |
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|
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/* |
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* SII hardware registers |
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*/ |
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typedef volatile struct { |
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u_short sdb; /* SCSI Data Bus and Parity */ |
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u_short pad0; |
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u_short sc1; /* SCSI Control Signals One */ |
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u_short pad1; |
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u_short sc2; /* SCSI Control Signals Two */ |
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u_short pad2; |
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u_short csr; /* Control/Status register */ |
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u_short pad3; |
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u_short id; /* Bus ID register */ |
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u_short pad4; |
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u_short slcsr; /* Select Control and Status Register */ |
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u_short pad5; |
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u_short destat; /* Selection Detector Status Register */ |
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u_short pad6; |
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u_short dstmo; /* DSSI Timeout Register */ |
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u_short pad7; |
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u_short data; /* Data Register */ |
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u_short pad8; |
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u_short dmctrl; /* DMA Control Register */ |
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u_short pad9; |
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u_short dmlotc; /* DMA Length of Transfer Counter */ |
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u_short pad10; |
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u_short dmaddrl; /* DMA Address Register Low */ |
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u_short pad11; |
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u_short dmaddrh; /* DMA Address Register High */ |
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u_short pad12; |
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u_short dmabyte; /* DMA Initial Byte Register */ |
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u_short pad13; |
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u_short stlp; /* DSSI Short Target List Pointer */ |
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u_short pad14; |
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u_short ltlp; /* DSSI Long Target List Pointer */ |
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u_short pad15; |
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u_short ilp; /* DSSI Initiator List Pointer */ |
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u_short pad16; |
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u_short dsctrl; /* DSSI Control Register */ |
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u_short pad17; |
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u_short cstat; /* Connection Status Register */ |
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u_short pad18; |
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u_short dstat; /* Data Transfer Status Register */ |
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u_short pad19; |
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u_short comm; /* Command Register */ |
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u_short pad20; |
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u_short dictrl; /* Diagnostic Control Register */ |
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u_short pad21; |
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u_short clock; /* Diagnostic Clock Register */ |
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u_short pad22; |
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u_short bhdiag; /* Bus Handler Diagnostic Register */ |
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u_short pad23; |
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u_short sidiag; /* SCSI IO Diagnostic Register */ |
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u_short pad24; |
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u_short dmdiag; /* Data Mover Diagnostic Register */ |
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u_short pad25; |
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u_short mcdiag; /* Main Control Diagnostic Register */ |
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u_short pad26; |
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} SIIRegs; |
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|
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/* |
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* SC1 - SCSI Control Signals One |
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*/ |
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#define SII_SC1_MSK 0x1ff /* All possible signals on the bus */ |
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#define SII_SC1_SEL 0x80 /* SCSI SEL signal active on bus */ |
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#define SII_SC1_ATN 0x08 /* SCSI ATN signal active on bus */ |
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|
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/* |
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* SC2 - SCSI Control Signals Two |
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*/ |
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#define SII_SC2_IGS 0x8 /* SCSI drivers for initiator mode */ |
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|
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/* |
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* CSR - Control/Status Register |
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*/ |
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#define SII_HPM 0x10 /* SII in on an arbitrated SCSI bus */ |
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#define SII_RSE 0x08 /* 1 = respond to reselections */ |
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#define SII_SLE 0x04 /* 1 = respond to selections */ |
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#define SII_PCE 0x02 /* 1 = report parity errors */ |
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#define SII_IE 0x01 /* 1 = enable interrupts */ |
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|
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/* |
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* ID - Bus ID Register |
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*/ |
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#define SII_ID_IO 0x8000 /* I/O */ |
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|
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/* |
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* DESTAT - Selection Detector Status Register |
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*/ |
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#define SII_IDMSK 0x7 /* ID of target reselected the SII */ |
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|
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/* |
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* DMCTRL - DMA Control Register |
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*/ |
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#define SII_ASYNC 0x00 /* REQ/ACK Offset for async mode */ |
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#define SII_SYNC 0x03 /* REQ/ACK Offset for sync mode */ |
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|
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/* |
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* DMLOTC - DMA Length Of Transfer Counter |
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*/ |
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#define SII_TCMSK 0x1fff /* transfer count mask */ |
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|
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/* |
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* CSTAT - Connection Status Register |
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*/ |
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#define SII_CI 0x8000 /* composite interrupt bit for CSTAT */ |
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#define SII_DI 0x4000 /* composite interrupt bit for DSTAT */ |
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#define SII_RST 0x2000 /* 1 if reset is asserted on SCSI bus */ |
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#define SII_BER 0x1000 /* Bus error */ |
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#define SII_OBC 0x0800 /* Out_en Bit Cleared (DSSI mode) */ |
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#define SII_TZ 0x0400 /* Target pointer Zero (STLP or LTLP is zero) */ |
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#define SII_BUF 0x0200 /* Buffer service - outbound pkt to non-DSSI */ |
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#define SII_LDN 0x0100 /* List element Done */ |
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#define SII_SCH 0x0080 /* State Change */ |
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#define SII_CON 0x0040 /* SII is Connected to another device */ |
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#define SII_DST 0x0020 /* SII was Destination of current transfer */ |
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#define SII_TGT 0x0010 /* SII is operating as a Target */ |
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#define SII_STATE_MSK 0x0070 /* State Mask */ |
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#define SII_SWA 0x0008 /* Selected With Attention */ |
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#define SII_SIP 0x0004 /* Selection In Progress */ |
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#define SII_LST 0x0002 /* Lost arbitration */ |
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|
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/* |
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* DSTAT - Data Transfer Status Register |
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*/ |
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#define SII_DNE 0x2000 /* DMA transfer Done */ |
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#define SII_TCZ 0x1000 /* Transfer Count register is Zero */ |
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#define SII_TBE 0x0800 /* Transmit Buffer Empty */ |
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#define SII_IBF 0x0400 /* Input Buffer Full */ |
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#define SII_IPE 0x0200 /* Incoming Parity Error */ |
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#define SII_OBB 0x0100 /* Odd Byte Boundry */ |
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#define SII_MIS 0x0010 /* Phase Mismatch */ |
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#define SII_ATN 0x0008 /* ATN set by initiator if in Target mode */ |
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#define SII_MSG 0x0004 /* current bus state of MSG */ |
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#define SII_CD 0x0002 /* current bus state of C/D */ |
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#define SII_IO 0x0001 /* current bus state of I/O */ |
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#define SII_PHASE_MSK 0x0007 /* Phase Mask */ |
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|
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/* |
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* The different phases. |
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*/ |
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#define SII_MSG_IN_PHASE 0x7 |
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#define SII_MSG_OUT_PHASE 0x6 |
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#define SII_STATUS_PHASE 0x3 |
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#define SII_CMD_PHASE 0x2 |
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#define SII_DATA_IN_PHASE 0x1 |
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#define SII_DATA_OUT_PHASE 0x0 |
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|
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/* |
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* COMM - Command Register |
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*/ |
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#define SII_DMA 0x8000 /* DMA mode */ |
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#define SII_DO_RST 0x4000 /* Assert reset on SCSI bus for 25 usecs */ |
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#define SII_RSL 0x1000 /* 0 = select, 1 = reselect desired device */ |
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|
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/* Commands: I - Initiator, T - Target, D - Disconnected */ |
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#define SII_INXFER 0x0800 /* Information Transfer command (I,T) */ |
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#define SII_SELECT 0x0400 /* Select command (D) */ |
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#define SII_REQDATA 0x0200 /* Request Data command (T) */ |
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#define SII_DISCON 0x0100 /* Disconnect command (I,T,D) */ |
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#define SII_CHRESET 0x0080 /* Chip Reset command (I,T,D) */ |
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|
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/* Command state bits same as connection status register */ |
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/* Command phase bits same as data transfer status register */ |
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|
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/* |
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* DICTRL - Diagnostic Control Register |
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*/ |
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#define SII_PRE 0x4 /* Enable the SII to drive the SCSI bus */ |
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|
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#define SII_WAIT_COUNT 10000 /* Delay count used for the SII chip */ |
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/* |
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* Max DMA transfer length for SII |
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* The SII chip only has a 13 bit counter. If 8192 is used as the max count, |
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* you can't tell the difference between a count of zero and 8192. |
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* 8190 is used instead of 8191 so the count is even. |
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*/ |
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#define SII_MAX_DMA_XFER_LENGTH 8192 |
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|
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#endif /* _SII */ |
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