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dpavlin |
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/* GXemul: $Id: sh4_scifreg.h,v 1.1 2006/10/19 10:15:57 debug Exp $ */ |
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/* $NetBSD: scifreg.h,v 1.10 2006/02/18 00:41:32 uwe Exp $ */ |
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#ifndef _SH3_SCIFREG_H_ |
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#define _SH3_SCIFREG_H_ |
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/*- |
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/* |
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* Serial Communication Interface with FIFO (SCIF) |
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*/ |
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#define SH3_SCIF0_BASE 0xa4000150 |
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#define SH3_SCIF1_BASE 0xa4000140 |
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#define SH4_SCIF_BASE 0xffe80000 |
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#ifdef SH3 |
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/* SH3 definitions */ |
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#define SCIF_SMR 0x0 /* serial mode */ |
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#define SCIF_BRR 0x2 /* bit rate */ |
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#define SCIF_SCR 0x4 /* serial control */ |
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#define SCIF_FTDR 0x6 /* transmit fifo data */ |
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#define SCIF_SSR 0x8 /* serial status */ |
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#define SCIF_FRDR 0xa /* receive fifo data */ |
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#define SCIF_FCR 0xc /* fifo control */ |
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#define SCIF_FDR 0xe /* fifo data count set */ |
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#define SHREG_SCSMR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_SMR)) |
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#define SHREG_SCBRR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_BRR)) |
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#define SHREG_SCSCR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_SCR)) |
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#define SHREG_SCFTDR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_FTDR)) |
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#define SHREG_SCSSR2 (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_SSR)) |
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#define SHREG_SCFRDR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_FRDR)) |
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#define SHREG_SCFCR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_FCR)) |
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#define SHREG_SCFDR2 (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_FDR)) |
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#else /* !SH3 */ |
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/* SH4 definitions */ |
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#define SCIF_SMR 0x00 /* serial mode */ |
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#define SCIF_BRR 0x04 /* bit rate */ |
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#define SCIF_SCR 0x08 /* serial control */ |
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#define SCIF_FTDR 0x0c /* transmit fifo data */ |
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#define SCIF_SSR 0x10 /* serial status */ |
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#define SCIF_FRDR 0x14 /* receive fifo data */ |
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#define SCIF_FCR 0x18 /* fifo control */ |
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#define SCIF_FDR 0x1c /* fifo data count set */ |
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#define SCIF_SPTR 0x20 /* seial port */ |
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#define SCIF_LSR 0x24 /* line status */ |
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#define SHREG_SCSMR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SMR)) |
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#define SHREG_SCBRR2 (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_BRR)) |
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#define SHREG_SCSCR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SCR)) |
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#define SHREG_SCFTDR2 (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FTDR)) |
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#define SHREG_SCSSR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SSR)) |
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#define SHREG_SCFRDR2 (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FRDR)) |
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#define SHREG_SCFCR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FCR)) |
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#define SHREG_SCFDR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FDR)) |
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#define SHREG_SCSPTR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SPTR)) |
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#define SHREG_SCLSR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_LSR)) |
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/* alias */ |
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#define SHREG_SCSFDR2 SHREG_SCFTDR2 |
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#define SHREG_SCFSR2 SHREG_SCSSR2 |
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#define SCSPTR2_RTSIO 0x0080 |
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#define SCSPTR2_RTSDT 0x0040 |
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#define SCSPTR2_CTSIO 0x0020 |
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#define SCSPTR2_CTSDT 0x0010 |
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#define SCSPTR2_SCKIO 0x0008 |
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#define SCSPTR2_SCKDT 0x0004 |
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#define SCSPTR2_SPB2IO 0x0002 |
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#define SCSPTR2_SPB2DT 0x0001 |
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#define SCLSR2_ORER 0x0001 /* overrun error */ |
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#endif /* !SH3 */ |
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/* SMR: serial mode */ |
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#define SCSMR2_CHR 0x40 /* character width (set = 7bit) */ |
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#define SCSMR2_PE 0x20 /* Parity Enable */ |
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#define SCSMR2_O 0x10 /* parity mode Odd */ |
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#define SCSMR2_STOP 0x08 /* STOP bit (set = 2 stop bits) */ |
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#define SCSMR2_CKS1 0x02 /* ClocK Select 1 */ |
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#define SCSMR2_CKS0 0x01 /* ClocK Select 0 */ |
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/* SMR: serial mode (for IrDA) */ |
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#define SCSMR2_IRMOD 0x80 /* IrDA mode */ |
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#define SCSMR2_ICK3 0x40 |
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#define SCSMR2_ICK2 0x20 |
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#define SCSMR2_ICK1 0x10 |
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#define SCSMR2_ICK0 0x08 |
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#define SCSMR2_PSEL 0x04 /* Pulse width SELelect */ |
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/* SCR: serial control */ |
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#define SCSCR2_TIE 0x80 /* Transmit Interrupt Enable */ |
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#define SCSCR2_RIE 0x40 /* Recieve Interrupt Enable */ |
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#define SCSCR2_TE 0x20 /* Transmit Enable */ |
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#define SCSCR2_RE 0x10 /* Receive Enable */ |
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#define SCSCR2_CKE1 0x02 /* ClocK Enable 1 */ |
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#define SCSCR2_CKE0 0x01 /* ClocK Enable 0 (not in sh4) */ |
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/* SSR: serial status */ |
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#define SCSSR2_ER 0x0080 /* ERror */ |
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#define SCSSR2_TEND 0x0040 /* Transmit END */ |
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#define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */ |
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#define SCSSR2_BRK 0x0010 /* BReaK detection */ |
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#define SCSSR2_FER 0x0008 /* Framing ERror */ |
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#define SCSSR2_PER 0x0004 /* Parity ERror */ |
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#define SCSSR2_RDF 0x0002 /* Recieve fifo Data Full */ |
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#define SCSSR2_DR 0x0001 /* Data Ready */ |
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/* FCR: fifo control */ |
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#define SCFCR2_RTRG1 0x80 /* Receive TRiGger 1 */ |
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#define SCFCR2_RTRG0 0x40 /* Receive TRiGger 0 */ |
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#define SCFCR2_TTRG1 0x20 /* Transmit TRiGger 1 */ |
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#define SCFCR2_TTRG0 0x10 /* Transmit TRiGger 0 */ |
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#define SCFCR2_MCE 0x08 /* Modem Control Enable */ |
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#define SCFCR2_TFRST 0x04 /* Transmit Fifo register ReSeT */ |
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#define SCFCR2_RFRST 0x02 /* Receive Fifo register ReSeT */ |
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#define SCFCR2_LOOP 0x01 /* LOOP back test */ |
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#define FIFO_RCV_TRIGGER_1 0x00 |
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#define FIFO_RCV_TRIGGER_4 0x40 |
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#define FIFO_RCV_TRIGGER_8 0x80 |
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#define FIFO_RCV_TRIGGER_14 0xc0 |
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#define FIFO_XMT_TRIGGER_8 0x00 |
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#define FIFO_XMT_TRIGGER_4 0x10 |
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#define FIFO_XMT_TRIGGER_2 0x20 |
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#define FIFO_XMT_TRIGGER_1 0x30 |
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/* FDR: fifo data count set */ |
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#define SCFDR2_TXCNT 0xff00 /* Tx CouNT */ |
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#define SCFDR2_RECVCNT 0x00ff /* Rx CouNT */ |
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#define SCFDR2_TXF_FULL 0x1000 /* Tx FULL */ |
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#define SCFDR2_RXF_EPTY 0x0000 /* Rx EMPTY */ |
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#endif /* !_SH3_SCIFREG_ */ |
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