1 |
/* GXemul: $Id: sh4_mmu.h,v 1.1 2006/09/23 03:51:06 debug Exp $ */ |
2 |
/* $NetBSD: mmu_sh4.h,v 1.6 2006/03/04 01:55:03 uwe Exp $ */ |
3 |
|
4 |
#ifndef _SH3_MMU_SH4_H_ |
5 |
#define _SH3_MMU_SH4_H_ |
6 |
|
7 |
/*- |
8 |
* Copyright (c) 2002 The NetBSD Foundation, Inc. |
9 |
* All rights reserved. |
10 |
* |
11 |
* This code is derived from software contributed to The NetBSD Foundation |
12 |
* by UCHIYAMA Yasushi. |
13 |
* |
14 |
* Redistribution and use in source and binary forms, with or without |
15 |
* modification, are permitted provided that the following conditions |
16 |
* are met: |
17 |
* 1. Redistributions of source code must retain the above copyright |
18 |
* notice, this list of conditions and the following disclaimer. |
19 |
* 2. Redistributions in binary form must reproduce the above copyright |
20 |
* notice, this list of conditions and the following disclaimer in the |
21 |
* documentation and/or other materials provided with the distribution. |
22 |
* 3. All advertising materials mentioning features or use of this software |
23 |
* must display the following acknowledgement: |
24 |
* This product includes software developed by the NetBSD |
25 |
* Foundation, Inc. and its contributors. |
26 |
* 4. Neither the name of The NetBSD Foundation nor the names of its |
27 |
* contributors may be used to endorse or promote products derived |
28 |
* from this software without specific prior written permission. |
29 |
* |
30 |
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
31 |
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
32 |
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
33 |
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
34 |
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
35 |
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
36 |
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
37 |
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
38 |
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
39 |
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
40 |
* POSSIBILITY OF SUCH DAMAGE. |
41 |
*/ |
42 |
|
43 |
/* #include <sh3/devreg.h> */ |
44 |
|
45 |
/* ITLB 4-entry full-associative UTLB 64-entry full-associative */ |
46 |
#define SH4_PTEH 0xff000000 |
47 |
#define SH4_PTEH_VPN_MASK 0xfffffc00 |
48 |
#define SH4_PTEH_ASID_MASK 0x000000ff |
49 |
#define SH4_PTEL 0xff000004 |
50 |
#define SH4_PTEL_WT 0x00000001 |
51 |
#define SH4_PTEL_SH 0x00000002 |
52 |
#define SH4_PTEL_D 0x00000004 |
53 |
#define SH4_PTEL_C 0x00000008 |
54 |
#define SH4_PTEL_PR_SHIFT 5 |
55 |
#define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */ |
56 |
#define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */ |
57 |
#define SH4_PTEL_SZ_1K 0x00000000 |
58 |
#define SH4_PTEL_SZ_4K 0x00000010 |
59 |
#define SH4_PTEL_SZ_64K 0x00000080 |
60 |
#define SH4_PTEL_SZ_1M 0x00000090 |
61 |
#define SH4_PTEL_V 0x00000100 |
62 |
#define SH4_PTEL_HWBITS 0x1ffff1ff /* [28:12]PFN [8:0]attr. */ |
63 |
|
64 |
#define SH4_PTEA 0xff000034 |
65 |
#define SH4_PTEA_SA_MASK 0x00000007 |
66 |
#define SH4_PTEA_SA_TC 0x00000008 |
67 |
#define SH4_TTB 0xff000008 |
68 |
#define SH4_TEA 0xff00000c |
69 |
#define SH4_MMUCR 0xff000010 |
70 |
#define SH4_MMUCR_AT 0x00000001 |
71 |
#define SH4_MMUCR_TI 0x00000004 |
72 |
#define SH4_MMUCR_SV 0x00000100 |
73 |
#define SH4_MMUCR_SQMD 0x00000200 |
74 |
#define SH4_MMUCR_URC_SHIFT 10 |
75 |
#define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */ |
76 |
#define SH4_MMUCR_URB_SHIFT 18 |
77 |
#define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */ |
78 |
#define SH4_MMUCR_LRUI_SHIFT 26 |
79 |
#define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */ |
80 |
|
81 |
#define SH4_MMUCR_MASK (SH4_MMUCR_LRUT_MASK | SH4_MMUCR_URB_MASK | \ |
82 |
SH4_MMUCR_URC_MASK | SH4_MMUCR_SQMD | SH4_MMUCR_SV | SH4_MMUCR_AT) |
83 |
/* |
84 |
* memory-mapped TLB |
85 |
* must be access from P2-area program. |
86 |
* branch to the other area must be maed at least 8 instruction |
87 |
* after access. |
88 |
*/ |
89 |
#define SH4_ITLB_ENTRY 4 |
90 |
#define SH4_UTLB_ENTRY 64 |
91 |
|
92 |
/* ITLB */ |
93 |
#define SH4_ITLB_AA 0xf2000000 |
94 |
/* address specification (common for address and data array(0,1)) */ |
95 |
#define SH4_ITLB_E_SHIFT 8 |
96 |
#define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */ |
97 |
/* data specification */ |
98 |
/* address-array */ |
99 |
#define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */ |
100 |
#define SH4_ITLB_AA_V 0x00000100 |
101 |
#define SH4_ITLB_AA_VPN_SHIFT 10 |
102 |
#define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ |
103 |
/* data-array 1 */ |
104 |
#define SH4_ITLB_DA1 0xf3000000 |
105 |
#define SH4_ITLB_DA1_SH 0x00000002 |
106 |
#define SH4_ITLB_DA1_C 0x00000008 |
107 |
#define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ |
108 |
#define SH4_ITLB_DA1_SZ_1K 0x00000000 |
109 |
#define SH4_ITLB_DA1_SZ_4K 0x00000010 |
110 |
#define SH4_ITLB_DA1_SZ_64K 0x00000080 |
111 |
#define SH4_ITLB_DA1_SZ_1M 0x00000090 |
112 |
#define SH4_ITLB_DA1_PR 0x00000040 |
113 |
#define SH4_ITLB_DA1_V 0x00000100 |
114 |
#define SH4_ITLB_DA1_PPN_SHIFT 11 |
115 |
#define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ |
116 |
/* data-array 2 */ |
117 |
#define SH4_ITLB_DA2 0xf3800000 |
118 |
#define SH4_ITLB_DA2_SA_MASK 0x00000003 |
119 |
#define SH4_ITLB_DA2_TC 0x00000004 |
120 |
|
121 |
/* UTLB */ |
122 |
#define SH4_UTLB_AA 0xf6000000 |
123 |
/* address specification (common for address and data array(0,1)) */ |
124 |
#define SH4_UTLB_E_SHIFT 8 |
125 |
#define SH4_UTLB_E_MASK 0x00003f00 |
126 |
#define SH4_UTLB_A 0x00000080 |
127 |
/* data specification */ |
128 |
/* address-array */ |
129 |
#define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ |
130 |
#define SH4_UTLB_AA_D 0x00000200 |
131 |
#define SH4_UTLB_AA_V 0x00000100 |
132 |
#define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */ |
133 |
/* data-array 1 */ |
134 |
#define SH4_UTLB_DA1 0xf7000000 |
135 |
#define SH4_UTLB_DA1_WT 0x00000001 |
136 |
#define SH4_UTLB_DA1_SH 0x00000002 |
137 |
#define SH4_UTLB_DA1_D 0x00000004 |
138 |
#define SH4_UTLB_DA1_C 0x00000008 |
139 |
#define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ |
140 |
#define SH4_UTLB_DA1_SZ_1K 0x00000000 |
141 |
#define SH4_UTLB_DA1_SZ_4K 0x00000010 |
142 |
#define SH4_UTLB_DA1_SZ_64K 0x00000080 |
143 |
#define SH4_UTLB_DA1_SZ_1M 0x00000090 |
144 |
#define SH4_UTLB_DA1_PR_SHIFT 5 |
145 |
#define SH4_UTLB_DA1_PR_MASK 0x00000060 |
146 |
#define SH4_UTLB_DA1_V 0x00000100 |
147 |
#define SH4_UTLB_DA1_PPN_SHIFT 11 |
148 |
#define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ |
149 |
/* data-array 2 */ |
150 |
#define SH4_UTLB_DA2 0xf7800000 |
151 |
#define SH4_UTLB_DA2_SA_MASK 0x00000003 |
152 |
#define SH4_UTLB_DA2_TC 0x00000004 |
153 |
|
154 |
#define SH4_TLB_DISABLE *(volatile uint32_t *)SH4_MMUCR = SH4_MMUCR_TI |
155 |
#endif /* !_SH3_MMU_SH4_H_ */ |