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dpavlin |
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/* GXemul: $Id: sh4_intcreg.h,v 1.1 2006/10/27 13:12:21 debug Exp $ */ |
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/* $NetBSD: intcreg.h,v 1.10 2005/12/11 12:18:58 christos Exp $ */ |
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#ifndef _SH3_INTCREG_H_ |
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#define _SH3_INTCREG_H_ |
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/*- |
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/* #include <sh3/devreg.h> */ |
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/* |
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* INTC |
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*/ |
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/* SH3 SH7708*, SH7709* common */ |
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#define SH3_ICR0 0xfffffee0 /* 16bit */ |
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#define SH3_IPRA 0xfffffee2 /* 16bit */ |
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#define SH3_IPRB 0xfffffee4 /* 16bit */ |
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/* SH7709, SH7709A only */ |
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#define SH7709_ICR1 0xa4000010 /* 16bit */ |
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#define SH7709_ICR2 0xa4000012 /* 16bit */ |
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#define SH7709_PINTER 0xa4000014 /* 16bit */ |
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#define SH7709_IPRC 0xa4000016 /* 16bit */ |
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#define SH7709_IPRD 0xa4000018 /* 16bit */ |
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#define SH7709_IPRE 0xa400001a /* 16bit */ |
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#define SH7709_IRR0 0xa4000004 /* 8bit */ |
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#define SH7709_IRR1 0xa4000006 /* 8bit */ |
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#define SH7709_IRR2 0xa4000008 /* 8bit */ |
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#define IPRC_IRQ3_MASK 0xf000 |
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#define IPRC_IRQ2_MASK 0x0f00 |
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#define IPRC_IRQ1_MASK 0x00f0 |
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#define IPRC_IRQ0_MASK 0x000f |
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#define IPRD_PINT07_MASK 0xf000 |
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#define IPRD_PINT8F_MASK 0x0f00 |
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#define IPRD_IRQ5_MASK 0x00f0 |
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#define IPRD_IRQ4_MASK 0x000f |
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#define IPRE_DMAC_MASK 0xf000 |
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#define IPRE_IRDA_MASK 0x0f00 |
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#define IPRE_SCIF_MASK 0x00f0 |
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#define IPRE_ADC_MASK 0x000f |
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#define IRR0_PINT8F 0x80 |
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#define IRR0_PINT07 0x40 |
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#define IRR0_IRQ5 0x20 |
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#define IRR0_IRQ4 0x10 |
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#define IRR0_IRQ3 0x08 |
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#define IRR0_IRQ2 0x04 |
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#define IRR0_IRQ1 0x02 |
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#define IRR0_IRQ0 0x01 |
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/* SH4 */ |
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#define SH4_ICR 0xffd00000 /* 16bit */ |
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#define SH4_IPRA 0xffd00004 /* 16bit */ |
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#define SH4_IPRB 0xffd00008 /* 16bit */ |
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#define SH4_IPRC 0xffd0000c /* 16bit */ |
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#define SH4_IPRD 0xffd00010 /* 16bit */ |
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#define SH4_INTPRI00 0xfe080000 /* 32bit */ |
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#define SH4_INTREQ00 0xfe080020 /* 32bit */ |
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#define SH4_INTMSK00 0xfe080040 /* 32bit */ |
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#define SH4_INTMSKCLR00 0xfe080060 /* 32bit */ |
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#define IPRC_GPIO_MASK 0xf000 |
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#define IPRC_DMAC_MASK 0x0f00 |
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#define IPRC_SCIF_MASK 0x00f0 |
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#define IPRC_HUDI_MASK 0x000f |
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#define IPRD_IRL0_MASK 0xf000 |
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#define IPRD_IRL1_MASK 0x0f00 |
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#define IPRD_IRL2_MASK 0x00f0 |
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#define IPRD_IRL3_MASK 0x000f |
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#define IPRA_TMU0_MASK 0xf000 |
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#define IPRA_TMU1_MASK 0x0f00 |
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#define IPRA_TMU2_MASK 0x00f0 |
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#define IPRA_RTC_MASK 0x000f |
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#define IPRB_WDT_MASK 0xf000 |
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#define IPRB_REF_MASK 0x0f00 |
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#define IPRB_SCI_MASK 0x00f0 |
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#define INTPRI00_PCI0_MASK 0x0000000f |
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#define INTPRI00_PCI1_MASK 0x000000f0 |
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#define INTPRI00_TMU3_MASK 0x00000f00 |
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#define INTPRI00_TMU4_MASK 0x0000f000 |
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/* INTREQ/INTMSK/INTMSKCLR */ |
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#define INTREQ00_PCISERR 0x00000001 |
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#define INTREQ00_PCIDMA3 0x00000002 |
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#define INTREQ00_PCIDMA2 0x00000004 |
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#define INTREQ00_PCIDMA1 0x00000008 |
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#define INTREQ00_PCIDMA0 0x00000010 |
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#define INTREQ00_PCIPWON 0x00000020 |
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#define INTREQ00_PCIPWDWN 0x00000040 |
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#define INTREQ00_PCIERR 0x00000080 |
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#define INTREQ00_TUNI3 0x00000100 |
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#define INTREQ00_TUNI4 0x00000200 |
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#define INTMSK00_MASK_ALL 0x000003ff |
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#endif /* !_SH3_INTCREG_H_ */ |
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