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dpavlin |
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/* GXemul: $Id: sh4_exception.h,v 1.1 2006/10/07 00:36:50 debug Exp $ */ |
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/* $NetBSD: exception.h,v 1.8 2006/03/04 01:55:03 uwe Exp $ */ |
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/*- |
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* Copyright (c) 2002 The NetBSD Foundation, Inc. |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the NetBSD |
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* Foundation, Inc. and its contributors. |
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* 4. Neither the name of The NetBSD Foundation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#ifndef _SH3_EXCEPTION_H_ |
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#define _SH3_EXCEPTION_H_ |
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/* |
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* SH3/SH4 Exception handling. |
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*/ |
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/* #include <sh3/devreg.h> */ |
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/* #ifdef _KERNEL */ |
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#define SH3_TRA 0xffffffd0 /* 32bit */ |
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#define SH3_EXPEVT 0xffffffd4 /* 32bit */ |
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#define SH3_INTEVT 0xffffffd8 /* 32bit */ |
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#define SH7709_INTEVT2 0xa4000000 /* 32bit */ |
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#define SH4_TRA 0xff000020 /* 32bit */ |
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#define SH4_EXPEVT 0xff000024 /* 32bit */ |
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#define SH4_INTEVT 0xff000028 /* 32bit */ |
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/* |
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* EXPEVT |
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*/ |
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/* Reset exception */ |
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#define EXPEVT_RESET_POWER 0x000 /* Power-On reset */ |
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#define EXPEVT_RESET_MANUAL 0x020 /* Manual reset */ |
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#define EXPEVT_RESET_TLB_MULTI_HIT 0x140 /* SH4 only */ |
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/* General exception */ |
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#define EXPEVT_TLB_MISS_LD 0x040 /* TLB miss (load) */ |
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#define EXPEVT_TLB_MISS_ST 0x060 /* TLB miss (store) */ |
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#define EXPEVT_TLB_MOD 0x080 /* Initial page write */ |
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#define EXPEVT_TLB_PROT_LD 0x0a0 /* Protection violation (load) */ |
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#define EXPEVT_TLB_PROT_ST 0x0c0 /* Protection violation (store)*/ |
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#define EXPEVT_ADDR_ERR_LD 0x0e0 /* Address error (load) */ |
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#define EXPEVT_ADDR_ERR_ST 0x100 /* Address error (store) */ |
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#define EXPEVT_FPU 0x120 /* FPU exception */ |
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#define EXPEVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */ |
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#define EXPEVT_RES_INST 0x180 /* Illegal instruction */ |
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#define EXPEVT_SLOT_INST 0x1a0 /* Illegal slot instruction */ |
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#define EXPEVT_BREAK 0x1e0 /* User break */ |
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#define EXPEVT_FPU_DISABLE 0x800 /* FPU disabled */ |
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#define EXPEVT_FPU_SLOT_DISABLE 0x820 /* Slot FPU disabled */ |
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/* Software bit */ |
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#define EXP_USER 0x001 /* exception from user-mode */ |
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#define _SH_TRA_BREAK 0xc3 /* magic number for debugger */ |
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/* |
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* INTEVT/INTEVT2 |
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*/ |
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/* External interrupt */ |
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#define SH_INTEVT_NMI 0x1c0 |
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#define SH_INTEVT_TMU0_TUNI0 0x400 |
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#define SH_INTEVT_TMU1_TUNI1 0x420 |
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#define SH_INTEVT_TMU2_TUNI2 0x440 |
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#define SH_INTEVT_TMU2_TICPI2 0x460 |
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#define SH_INTEVT_SCI_ERI 0x4e0 |
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#define SH_INTEVT_SCI_RXI 0x500 |
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#define SH_INTEVT_SCI_TXI 0x520 |
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#define SH_INTEVT_SCI_TEI 0x540 |
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#define SH_INTEVT_WDT_ITI 0x560 |
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#define SH_INTEVT_IRL9 0x320 |
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#define SH_INTEVT_IRL11 0x360 |
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#define SH_INTEVT_IRL13 0x3a0 |
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#define SH4_INTEVT_SCIF_ERI 0x700 |
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#define SH4_INTEVT_SCIF_RXI 0x720 |
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#define SH4_INTEVT_SCIF_BRI 0x740 |
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#define SH4_INTEVT_SCIF_TXI 0x760 |
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#define SH7709_INTEVT2_IRQ0 0x600 |
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#define SH7709_INTEVT2_IRQ1 0x620 |
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#define SH7709_INTEVT2_IRQ2 0x640 |
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#define SH7709_INTEVT2_IRQ3 0x660 |
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#define SH7709_INTEVT2_IRQ4 0x680 |
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#define SH7709_INTEVT2_IRQ5 0x6a0 |
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#define SH7709_INTEVT2_PINT07 0x700 |
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#define SH7709_INTEVT2_PINT8F 0x720 |
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#define SH7709_INTEVT2_DEI0 0x800 |
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#define SH7709_INTEVT2_DEI1 0x820 |
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#define SH7709_INTEVT2_DEI2 0x840 |
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#define SH7709_INTEVT2_DEI3 0x860 |
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#define SH7709_INTEVT2_IRDA_ERI 0x880 |
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#define SH7709_INTEVT2_IRDA_RXI 0x8a0 |
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#define SH7709_INTEVT2_IRDA_BRI 0x8c0 |
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#define SH7709_INTEVT2_IRDA_TXI 0x8e0 |
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#define SH7709_INTEVT2_SCIF_ERI 0x900 |
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#define SH7709_INTEVT2_SCIF_RXI 0x920 |
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#define SH7709_INTEVT2_SCIF_BRI 0x940 |
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#define SH7709_INTEVT2_SCIF_TXI 0x960 |
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#define SH7709_INTEVT2_ADC 0x980 |
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/* SH7750R, SH7751, SH7751R */ |
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#define SH4_INTEVT_IRL0 0x240 |
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#define SH4_INTEVT_IRL1 0x2a0 |
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#define SH4_INTEVT_IRL2 0x300 |
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#define SH4_INTEVT_IRL3 0x360 |
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#define SH4_INTEVT_IRQ0 0x200 |
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#define SH4_INTEVT_IRQ1 0x220 |
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#define SH4_INTEVT_IRQ2 0x240 |
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#define SH4_INTEVT_IRQ3 0x260 |
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#define SH4_INTEVT_IRQ4 0x280 |
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#define SH4_INTEVT_IRQ5 0x2a0 |
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#define SH4_INTEVT_IRQ6 0x2c0 |
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#define SH4_INTEVT_IRQ7 0x2e0 |
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#define SH4_INTEVT_IRQ8 0x300 |
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#define SH4_INTEVT_IRQ9 0x320 |
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#define SH4_INTEVT_IRQ10 0x340 |
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#define SH4_INTEVT_IRQ11 0x360 |
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#define SH4_INTEVT_IRQ12 0x380 |
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#define SH4_INTEVT_IRQ13 0x3a0 |
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#define SH4_INTEVT_IRQ14 0x3c0 |
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#define SH4_INTEVT_IRQ15 0x3e0 |
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#define SH4_INTEVT_TMU3 0xb00 |
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#define SH4_INTEVT_TMU4 0xb80 |
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#define SH4_INTEVT_PCISERR 0xa00 |
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#define SH4_INTEVT_PCIERR 0xae0 |
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#define SH4_INTEVT_PCIPWDWN 0xac0 |
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#define SH4_INTEVT_PCIPWON 0xaa0 |
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#define SH4_INTEVT_PCIDMA0 0xa80 |
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#define SH4_INTEVT_PCIDMA1 0xa60 |
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#define SH4_INTEVT_PCIDMA2 0xa40 |
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#define SH4_INTEVT_PCIDMA3 0xa20 |
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#ifndef _LOCORE |
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#if defined(SH3) && defined(SH4) |
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extern uint32_t __sh_TRA; |
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extern uint32_t __sh_EXPEVT; |
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extern uint32_t __sh_INTEVT; |
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#endif /* SH3 && SH4 */ |
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#endif /* !_LOCORE */ |
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/* #endif KERNEL */ |
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#endif /* !_SH3_EXCEPTION_H_ */ |
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