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#ifndef SH4_DMACREG_H |
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#define SH4_DMACREG_H |
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|
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/* |
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* Copyright (C) 2006-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: sh4_dmacreg.h,v 1.2 2006/12/30 13:31:01 debug Exp $ |
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* |
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* SH4 DMAC (DMA Controller) registers, as listed in the SH-7750 manual. |
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*/ |
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|
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#define N_SH4_DMA_CHANNELS 4 |
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|
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#define SH4_SAR0 0xffa00000 /* Source Address Register */ |
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#define SH4_DAR0 0xffa00004 /* Destination Address Register */ |
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#define SH4_DMATCR0 0xffa00008 /* Transfer Count Register */ |
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#define SH4_CHCR0 0xffa0000c /* Channel Control Register */ |
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|
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#define SH4_SAR1 0xffa00010 |
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#define SH4_DAR1 0xffa00014 |
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#define SH4_DMATCR1 0xffa00018 |
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#define SH4_CHCR1 0xffa0001c |
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|
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#define SH4_SAR2 0xffa00020 |
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#define SH4_DAR2 0xffa00024 |
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#define SH4_DMATCR2 0xffa00028 |
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#define SH4_CHCR2 0xffa0002c |
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|
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#define SH4_SAR3 0xffa00030 |
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#define SH4_DAR3 0xffa00034 |
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#define SH4_DMATCR3 0xffa00038 |
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#define SH4_CHCR3 0xffa0003c |
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|
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|
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/* |
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* Channel Control Register bit definitions: |
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*/ |
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|
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/* Source Address Space Attribute Specification: */ |
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/* (Only valid for PCMCIA access, in areas 5 and 6.) */ |
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#define CHCR_SSA_MASK 0xe0000000 |
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#define CHCR_SSA_RESERVED (0 << 29) |
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#define CHCR_SSA_DYNAMIC_BUS_SIZING (1 << 29) |
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#define CHCR_SSA_8BIT_IO_SPACE (2 << 29) |
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#define CHCR_SSA_16BIT_IO_SPACE (3 << 29) |
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#define CHCR_SSA_8BIT_COMMON_MEMORY_SPACE (4 << 29) |
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#define CHCR_SSA_16BIT_COMMON_MEMORY_SPACE (5 << 29) |
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#define CHCR_SSA_8BIT_ATTRIBUTE_MEMORY_SPACE (6 << 29) |
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#define CHCR_SSA_16BIT_ATTRIBUTE_MEMORY_SPACE (7 << 29) |
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#define CHCR_STC 0x10000000 |
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#define CHCR_DSA_MASK 0x0e000000 |
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#define CHCR_DTC 0x01000000 |
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#define CHCR_DS 0x00080000 |
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#define CHCR_RL 0x00040000 |
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#define CHCR_AM 0x00020000 |
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#define CHCR_AL 0x00010000 |
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#define CHCR_DM 0x0000c000 |
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#define CHCR_SM 0x00003000 |
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#define CHCR_RS 0x00000f00 |
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#define CHCR_TM 0x00000080 |
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#define CHCR_TS 0x00000070 |
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#define CHCR_IE 0x00000004 |
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#define CHCR_TE 0x00000002 |
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#define CHCR_TD 0x00000001 |
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|
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#define SH4_DMAOR 0xffa00040 /* DMA operation register */ |
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|
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#endif /* SH4_DMACREG_H */ |