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/* GXemul: $Id: sh4_bscreg.h,v 1.3 2006/11/11 01:02:17 debug Exp $ */ |
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/* $NetBSD: bscreg.h,v 1.6 2005/12/11 12:18:58 christos Exp $ */ |
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|
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/* This file has been extended with useful bitfield definitions from |
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the SH7750 manual. */ |
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|
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#ifndef _SH3_BSCREG_H_ |
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#define _SH3_BSCREG_H_ |
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|
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/*- |
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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|
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/* #include <sh3/devreg.h> */ |
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|
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/* |
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* Bus State Controller |
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*/ |
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|
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#define SH3_BCR1 0xffffff60 /* 16bit */ |
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#define SH3_BCR2 0xffffff62 /* 16bit */ |
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#define SH3_WCR1 0xffffff64 /* 16bit */ |
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#define SH3_WCR2 0xffffff66 /* 16bit */ |
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#define SH3_MCR 0xffffff68 /* 16bit */ |
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#define SH3_DCR 0xffffff6a /* 16bit */ |
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#define SH3_PCR 0xffffff6c /* 16bit */ |
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#define SH3_RTCSR 0xffffff6e /* 16bit */ |
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#define SH3_RTCNT 0xffffff70 /* 16bit */ |
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#define SH3_RTCOR 0xffffff72 /* 16bit */ |
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#define SH3_RFCR 0xffffff74 /* 16bit */ |
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#define SH3_BCR3 0xffffff7e /* 16bit */ |
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|
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#define SH4_BCR1 0xff800000 /* 32bit */ |
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#define SH4_BCR2 0xff800004 /* 16bit */ |
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#define SH4_WCR1 0xff800008 /* 32bit */ |
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#define SH4_WCR2 0xff80000c /* 32bit */ |
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#define SH4_WCR3 0xff800010 /* 32bit */ |
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#define SH4_MCR 0xff800014 /* 32bit */ |
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#define SH4_PCR 0xff800018 /* 16bit */ |
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#define SH4_RTCSR 0xff80001c /* 16bit */ |
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#define SH4_RTCNT 0xff800020 /* 16bit */ |
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#define SH4_RTCOR 0xff800024 /* 16bit */ |
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#define SH4_RFCR 0xff800028 /* 16bit */ |
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#define SH4_UNKNOWN_2C 0xff80002c /* ??? */ |
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#define SH4_UNKNOWN_30 0xff800030 /* ??? */ |
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#define SH4_BCR3 0xff800050 /* 16bit: SH7751R */ |
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#define SH4_BCR4 0xfe0a00f0 /* 32bit: SH7751R */ |
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|
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#define BCR1_LITTLE_ENDIAN (1 << 31) |
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#define BCR1_MASTER (1 << 30) |
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#define BCR1_BREQEN (1 << 19) |
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|
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#define BCR2_PORTEN (1 << 0) |
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|
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#define RTCSR_CMF (1 << 7) |
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#define RTCSR_CMIE (1 << 6) |
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#define RTCSR_CKS 0x0038 |
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#define RTCSR_OVF (1 << 2) |
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#define RTCSR_OVIE (1 << 1) |
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#define RTCSR_LMTS (1 << 0) |
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|
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#endif /* !_SH3_BSCREG_H_ */ |
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