| 1 |
/* GXemul: $Id: sgi_macereg.h,v 1.2 2007/01/20 16:11:26 debug Exp $ */ |
| 2 |
/* $NetBSD: macereg.h,v 1.2 2005/12/11 12:18:54 christos Exp $ */ |
| 3 |
|
| 4 |
#ifndef SGI_MACEREG_H |
| 5 |
#define SGI_MACEREG_H |
| 6 |
|
| 7 |
/* |
| 8 |
* Copyright (c) 2000 Soren S. Jorvang |
| 9 |
* All rights reserved. |
| 10 |
* |
| 11 |
* Redistribution and use in source and binary forms, with or without |
| 12 |
* modification, are permitted provided that the following conditions |
| 13 |
* are met: |
| 14 |
* 1. Redistributions of source code must retain the above copyright |
| 15 |
* notice, this list of conditions and the following disclaimer. |
| 16 |
* 2. Redistributions in binary form must reproduce the above copyright |
| 17 |
* notice, this list of conditions and the following disclaimer in the |
| 18 |
* documentation and/or other materials provided with the distribution. |
| 19 |
* 3. All advertising materials mentioning features or use of this software |
| 20 |
* must display the following acknowledgement: |
| 21 |
* This product includes software developed for the |
| 22 |
* NetBSD Project. See http://www.NetBSD.org/ for |
| 23 |
* information about NetBSD. |
| 24 |
* 4. The name of the author may not be used to endorse or promote products |
| 25 |
* derived from this software without specific prior written permission. |
| 26 |
* |
| 27 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 28 |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 29 |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 30 |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 31 |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 32 |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 33 |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 34 |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 35 |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 36 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 37 |
*/ |
| 38 |
|
| 39 |
#define MACE_BASE 0x1f000000 |
| 40 |
|
| 41 |
/* PCI definitions (offset 0x080000) */ |
| 42 |
|
| 43 |
#define MACE_PCI_ERROR_ADDR 0x00 |
| 44 |
#define MACE_PCI_ERROR_FLAGS 0x04 |
| 45 |
|
| 46 |
#define MACE_PCI_CONTROL 0x08 |
| 47 |
#define MACE_PCI_CONTROL_INT_MASK 0x000000ff |
| 48 |
#define MACE_PCI_CONTROL_SERR_ENA 0x00000100 |
| 49 |
#define MACE_PCI_CONTROL_ARB_N6 0x00000200 |
| 50 |
#define MACE_PCI_CONTROL_PARITY_ERR 0x00000400 |
| 51 |
#define MACE_PCI_CONTROL_MRMRA_ENA 0x00000800 |
| 52 |
#define MACE_PCI_CONTROL_ARB_N3 0x00001000 |
| 53 |
#define MACE_PCI_CONTROL_ARB_N4 0x00002000 |
| 54 |
#define MACE_PCI_CONTROL_ARB_N5 0x00004000 |
| 55 |
#define MACE_PCI_CONTROL_PARK_LIU 0x00008000 |
| 56 |
|
| 57 |
#define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000 |
| 58 |
#define MACE_PCI_CONTROL_OVERRUN_INT 0x01000000 |
| 59 |
#define MACE_PCI_CONTROL_PARITY_INT 0x02000000 |
| 60 |
#define MACE_PCI_CONTROL_SERR_INT 0x04000000 |
| 61 |
#define MACE_PCI_CONTROL_IT_INT 0x08000000 |
| 62 |
#define MACE_PCI_CONTROL_RE_INT 0x10000000 |
| 63 |
#define MACE_PCI_CONTROL_DPED_INT 0x20000000 |
| 64 |
#define MACE_PCI_CONTROL_TAR_INT 0x40000000 |
| 65 |
#define MACE_PCI_CONTROL_MAR_INT 0x80000000 |
| 66 |
|
| 67 |
|
| 68 |
#define MACE_PCI_REV_INFO_R 0x0c |
| 69 |
#define MACE_PCI_FLUSH_W 0x0c |
| 70 |
#define MACE_PCI_CONFIG_ADDR 0xcf8 |
| 71 |
#define MACE_PCI_CONFIG_DATA 0xcfc |
| 72 |
#define MACE_PCI_LOW_MEMORY 0x1a000000 |
| 73 |
#define MACE_PCI_LOW_IO 0x18000000 |
| 74 |
#define MACE_PCI_NATIVE_VIEW 0x40000000 |
| 75 |
#define MACE_PCI_IO 0x80000000 |
| 76 |
#define MACE_PCI_HI_MEMORY 0x280000000 |
| 77 |
#define MACE_PCI_HI_IO 0x100000000 |
| 78 |
|
| 79 |
#define MACE_VIN1 0x100000 |
| 80 |
#define MACE_VIN2 0x180000 |
| 81 |
#define MACE_VOUT 0x200000 |
| 82 |
#define MACE_PERIF 0x300000 |
| 83 |
#define MACE_ISA_EXT 0x380000 |
| 84 |
|
| 85 |
#if 1 |
| 86 |
/* GXemul, making it easier to use offsets further down: */ |
| 87 |
#define MACE_AUDIO 0 |
| 88 |
#define MACE_ISA 0 |
| 89 |
#define MACE_KBDMS 0 |
| 90 |
#define MACE_I2C 0 |
| 91 |
#define MACE_UST_MSC 0 |
| 92 |
#else |
| 93 |
#define MACE_AUDIO (MACE_PERIF + 0x00000) |
| 94 |
#define MACE_ISA (MACE_PERIF + 0x10000) |
| 95 |
#define MACE_KBDMS (MACE_PERIF + 0x20000) |
| 96 |
#define MACE_I2C (MACE_PERIF + 0x30000) |
| 97 |
#define MACE_UST_MSC (MACE_PERIF + 0x40000) |
| 98 |
#endif |
| 99 |
|
| 100 |
|
| 101 |
/*********************** |
| 102 |
* PCI_ERROR_FLAGS Bits |
| 103 |
*/ |
| 104 |
#define MACE_PERR_MASTER_ABORT 0x80000000 |
| 105 |
#define MACE_PERR_TARGET_ABORT 0x40000000 |
| 106 |
#define MACE_PERR_DATA_PARITY_ERR 0x20000000 |
| 107 |
#define MACE_PERR_RETRY_ERR 0x10000000 |
| 108 |
#define MACE_PERR_ILLEGAL_CMD 0x08000000 |
| 109 |
#define MACE_PERR_SYSTEM_ERR 0x04000000 |
| 110 |
#define MACE_PERR_INTERRUPT_TEST 0x02000000 |
| 111 |
#define MACE_PERR_PARITY_ERR 0x01000000 |
| 112 |
#define MACE_PERR_OVERRUN 0x00800000 |
| 113 |
#define MACE_PERR_RSVD 0x00400000 |
| 114 |
#define MACE_PERR_MEMORY_ADDR 0x00200000 |
| 115 |
#define MACE_PERR_CONFIG_ADDR 0x00100000 |
| 116 |
#define MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000 |
| 117 |
#define MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000 |
| 118 |
#define MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000 |
| 119 |
#define MACE_PERR_RETRY_ADDR_VALID 0x00010000 |
| 120 |
|
| 121 |
|
| 122 |
/******************************* |
| 123 |
* MACE ISA External Address Map |
| 124 |
*/ |
| 125 |
#define MACE_ISA_EPP_BASE (MACE_ISA_EXT + 0x00000) |
| 126 |
#define MACE_ISA_ECP_BASE (MACE_ISA_EXT + 0x08000) |
| 127 |
#define MACE_ISA_SER1_BASE (MACE_ISA_EXT + 0x10000) |
| 128 |
#define MACE_ISA_SER2_BASE (MACE_ISA_EXT + 0x18000) |
| 129 |
#define MACE_ISA_RTC_BASE (MACE_ISA_EXT + 0x20000) |
| 130 |
#define MACE_ISA_GAME_BASE (MACE_ISA_EXT + 0x30000) |
| 131 |
|
| 132 |
|
| 133 |
/************************* |
| 134 |
* ISA Interface Registers |
| 135 |
*/ |
| 136 |
|
| 137 |
/* ISA Ringbase Address and Reset Register */ |
| 138 |
|
| 139 |
#define MACE_ISA_RINGBASE (MACE_ISA + 0x0000) |
| 140 |
|
| 141 |
/* Flash-ROM/LED/DP-RAM/NIC Controller Register */ |
| 142 |
|
| 143 |
#define MACE_ISA_FLASH_NIC_REG (MACE_ISA + 0x0008) |
| 144 |
#define MACE_ISA_FLASH_WE 0x01 /* 1=> Enable FLASH writes */ |
| 145 |
#define MACE_ISA_PWD_CLEAR 0x02 /* 1=> PWD CLEAR jumper detected */ |
| 146 |
#define MACE_ISA_NIC_DEASSERT 0x04 |
| 147 |
#define MACE_ISA_NIC_DATA 0x08 |
| 148 |
#define MACE_ISA_LED_RED 0x10 /* 1=> Illuminate RED LED */ |
| 149 |
#define MACE_ISA_LED_GREEN 0x20 /* 1=> Illuminate GREEN LED */ |
| 150 |
#define MACE_ISA_DP_RAM_ENABLE 0x40 |
| 151 |
|
| 152 |
/* Interrupt Status and Mask Registers (32 bits) */ |
| 153 |
|
| 154 |
#define MACE_ISA_INT_STATUS (MACE_ISA + 0x0010) |
| 155 |
#define MACE_ISA_INT_MASK (MACE_ISA + 0x0018) |
| 156 |
|
| 157 |
/* bit definitions */ |
| 158 |
#define MACE_ISA_INT_RTC_IRQ 0x00000100 |
| 159 |
|
| 160 |
|
| 161 |
/******************************** |
| 162 |
* MACE Timer Interface Registers |
| 163 |
* |
| 164 |
* Note: MSC_UST<31:0> is MSC, MSC_UST<63:32> is UST. |
| 165 |
*/ |
| 166 |
#define MACE_UST (MACE_UST_MSC + 0x00) /* Universial system time */ |
| 167 |
#define MACE_COMPARE1 (MACE_UST_MSC + 0x08) /* Interrupt compare reg 1 */ |
| 168 |
#define MACE_COMPARE2 (MACE_UST_MSC + 0x10) /* Interrupt compare reg 2 */ |
| 169 |
#define MACE_COMPARE3 (MACE_UST_MSC + 0x18) /* Interrupt compare reg 3 */ |
| 170 |
#define MACE_UST_PERIOD 960 /* UST Period in ns */ |
| 171 |
|
| 172 |
#define MACE_AIN_MSC_UST (MACE_UST_MSC + 0x20) /* Audio in MSC/UST pair */ |
| 173 |
#define MACE_AOUT1_MSC_UST (MACE_UST_MSC + 0x28) /* Audio out 1 MSC/UST pair */ |
| 174 |
#define MACE_AOUT2_MSC_UST (MACE_UST_MSC + 0x30) /* Audio out 2 MSC/UST pair */ |
| 175 |
#define MACE_VIN1_MSC_UST (MACE_UST_MSC + 0x38) /* Video In 1 MSC/UST pair */ |
| 176 |
#define MACE_VIN2_MSC_UST (MACE_UST_MSC + 0x40) /* Video In 2 MSC/UST pair */ |
| 177 |
#define MACE_VOUT_MSC_UST (MACE_UST_MSC + 0x48) /* Video out MSC/UST pair */ |
| 178 |
|
| 179 |
#endif /* SGI_MACEREG_H */ |
Parent Directory
| 
Revision Log