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dpavlin |
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/* gxemul: $Id: pica.h,v 1.3 2005/03/05 12:34:03 debug Exp $ */ |
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/* $NetBSD: pica.h,v 1.2 2001/06/13 15:11:38 soda Exp $ */ |
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/* $OpenBSD: pica.h,v 1.4 1996/09/14 15:58:28 pefo Exp $ */ |
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#ifndef _PICA_H_ |
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#define _PICA_H_ 1 |
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#define RELATIVE |
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/* |
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* Copyright (c) 1994, 1995, 1996 Per Fogelstrom |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed under OpenBSD by |
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* Per Fogelstrom. |
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* 4. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS |
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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*/ |
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/* |
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* PICA's Physical address space |
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*/ |
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#define PICA_PHYS_MIN 0x00000000 /* 256 Meg */ |
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#define PICA_PHYS_MAX 0x0fffffff |
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/* |
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* Memory map |
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*/ |
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#define PICA_PHYS_MEMORY_START 0x00000000 |
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#define PICA_PHYS_MEMORY_END 0x0fffffff /* 256 Meg in 8 slots */ |
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#define PICA_MEMORY_SIZE_REG 0xe00fffe0 /* Memory size register */ |
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#define PICA_CONFIG_REG 0xe00ffff0 /* Hardware config reg */ |
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/* |
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* I/O map |
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*/ |
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#define R4030_P_LOCAL_IO_BASE 0x80000000 /* I/O Base address */ |
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#define R4030_V_LOCAL_IO_BASE 0xe0000000 |
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#define R4030_S_LOCAL_IO_BASE 0x00040000 /* Size */ |
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#ifndef RELATIVE |
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#define R4030 R4030_V_LOCAL_IO_BASE |
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#else |
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#define R4030 0 |
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#endif |
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#define R4030_SYS_CONFIG (R4030+0x0000) /* Global config register */ |
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#define R4030_SYS_TL_BASE (R4030+0x0018) /* DMA transl. table base */ |
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#define R4030_SYS_TL_LIMIT (R4030+0x0020) /* DMA transl. table limit */ |
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#define R4030_SYS_TL_IVALID (R4030+0x0028) /* DMA transl. cache inval */ |
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#define R4030_SYS_DMA0_REGS (R4030+0x0100) /* DMA ch0 base address */ |
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#define R4030_SYS_DMA1_REGS (R4030+0x0120) /* DMA ch0 base address */ |
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#define R4030_SYS_DMA2_REGS (R4030+0x0140) /* DMA ch0 base address */ |
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#define R4030_SYS_DMA3_REGS (R4030+0x0160) /* DMA ch0 base address */ |
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#define R4030_SYS_DMA_INT_SRC (R4030+0x0200) /* DMA int source status reg */ |
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#define R4030_SYS_NVRAM_PROT (R4030+0x0220) /* NV ram protect register */ |
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#define R4030_SYS_IT_VALUE (R4030+0x0228) /* Interval timer reload */ |
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#define R4030_SYS_IT_STAT (R4030+0x0230) /* Interval timer count */ |
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#define R4030_SYS_ISA_VECTOR (R4030+0x0238) /* ISA Interrupt vector */ |
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#define R4030_SYS_EXT_IMASK (R4030+0x00e8) /* External int enable mask */ |
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#ifndef RELATIVE |
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#define PVLB R4030_V_LOCAL_IO_BASE |
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#else |
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#define PVLB 0 |
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#endif |
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#define PICA_SYS_SONIC (PVLB+0x1000) /* SONIC base address */ |
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#define PICA_SYS_SCSI (PVLB+0x2000) /* SCSI base address */ |
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#define PICA_SYS_FLOPPY (PVLB+0x3000) /* Floppy base address */ |
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#define PICA_SYS_CLOCK (PVLB+0x4000) /* Clock base address */ |
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#define PICA_SYS_KBD (PVLB+0x5000) /* Keybrd/mouse base address */ |
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#define PICA_SYS_COM1 (PVLB+0x6000) /* Com port 1 */ |
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#define PICA_SYS_COM2 (PVLB+0x7000) /* Com port 2 */ |
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#define PICA_SYS_PAR1 (PVLB+0x8000) /* Parallel port 1 */ |
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#define PICA_SYS_NVRAM (PVLB+0x9000) /* Unprotected NV-ram */ |
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#define PICA_SYS_PNVRAM (PVLB+0xa000) /* Protected NV-ram */ |
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#define PICA_SYS_NVPROM (PVLB+0xb000) /* Read only NV-ram */ |
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#define PICA_SYS_SOUND (PVLB+0xc000) /* Sound port */ |
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#define PICA_SYS_ISA_AS (PICA_V_ISA_IO+0x70) |
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#define PICA_P_DRAM_CONF 0x800e0000 /* Dram config registers */ |
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#define PICA_V_DRAM_CONF 0xe00e0000 |
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#define PICA_S_DRAM_CONF 0x00020000 |
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#define PICA_P_INT_SOURCE 0xf0000000 /* Interrupt src registers */ |
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#define PICA_V_INT_SOURCE R4030_V_LOCAL_IO_BASE+R4030_S_LOCAL_IO_BASE |
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#define PICA_S_INT_SOURCE 0x00001000 |
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#define PVIS PICA_V_INT_SOURCE |
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#define PICA_SYS_LB_IS (PVIS+0x0000) /* Local bus int source */ |
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#define PICA_SYS_LB_IE (PVIS+0x0002) /* Local bus int enables */ |
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#define PICA_P_LOCAL_VIDEO_CTRL 0x60000000 /* Local video control */ |
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#define PICA_V_LOCAL_VIDEO_CTRL 0xe0200000 |
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#define PICA_S_LOCAL_VIDEO_CTRL 0x00200000 |
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#define PICA_P_EXTND_VIDEO_CTRL 0x60200000 /* Extended video control */ |
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#define PICA_V_EXTND_VIDEO_CTRL 0xe0400000 |
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#define PICA_S_EXTND_VIDEO_CTRL 0x00200000 |
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#define PICA_P_LOCAL_VIDEO 0x40000000 /* Local video memory */ |
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#define PICA_V_LOCAL_VIDEO 0xe0800000 |
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#define PICA_S_LOCAL_VIDEO 0x00800000 |
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#define PICA_P_ISA_IO 0x90000000 /* ISA I/O control */ |
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#define PICA_V_ISA_IO 0xe2000000 |
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#define PICA_S_ISA_IO 0x01000000 |
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#define PICA_P_ISA_MEM 0x91000000 /* ISA Memory control */ |
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#define PICA_V_ISA_MEM 0xe3000000 |
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#define PICA_S_ISA_MEM 0x01000000 |
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/* |
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* Addresses used by various display drivers. |
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*/ |
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#define PICA_MONO_BASE (PICA_V_LOCAL_VIDEO_CTRL + 0x3B4) |
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#define PICA_MONO_BUF (PICA_V_LOCAL_VIDEO + 0xB0000) |
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#define PICA_CGA_BASE (PICA_V_LOCAL_VIDEO_CTRL + 0x3D4) |
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#define PICA_CGA_BUF (PICA_V_LOCAL_VIDEO + 0xB8000) |
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#endif /* _PICA_H_ */ |
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