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#ifndef OPCODES_MIPS_H |
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#define OPCODES_MIPS_H |
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|
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/* |
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* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: opcodes_mips.h,v 1.16 2006/12/30 13:31:01 debug Exp $ |
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* |
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* MIPS opcodes, gathered from various sources. |
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* |
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* There are quite a number of different MIPS instruction sets, some are |
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* subsets/supersets of others, but not all of them. |
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* |
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* MIPS ISA I, II, III, IV: Backward-compatible ISAs used in R2000/R3000 |
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* (ISA I), R6000 (ISA II), R4000 (ISA III), |
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* and R5000/R1x000 (ISA IV). |
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* |
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* MIPS ISA V: Never implemented in hardware? |
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* |
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* MIPS32 and MIPS64: The "modern" version of the ISA. These exist |
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* in a revision 1, and a revision 2 (the latest |
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* at the time of writing this). |
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* |
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* MIPS16: A special encoding form for MIPS32/64 which |
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* uses 16-bit instruction words instead of |
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* 32-bit. |
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* |
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* MDMX: MIPS Digital Media Extension. |
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* |
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* MIPS 3D: 3D instructions. |
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* |
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* MIPS MT: Multi-Threaded stuff. |
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*/ |
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|
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|
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/* Opcodes: */ |
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|
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#define HI6_NAMES { \ |
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"special", "regimm", "j", "jal", "beq", "bne", "blez", "bgtz", /* 0x00 - 0x07 */ \ |
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"addi", "addiu", "slti", "sltiu", "andi", "ori", "xori", "lui", /* 0x08 - 0x0f */ \ |
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"cop0", "cop1", "cop2", "cop3", "beql", "bnel", "blezl", "bgtzl", /* 0x10 - 0x17 */ \ |
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"daddi", "daddiu", "ldl", "ldr", "special2", "hi6_1d","lq" /*mdmx*/, "sq" /*special3*/, /* 0x18 - 0x1f */\ |
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"lb", "lh", "lwl", "lw", "lbu", "lhu", "lwr", "lwu", /* 0x20 - 0x27 */ \ |
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"sb", "sh", "swl", "sw", "sdl", "sdr", "swr", "cache", /* 0x28 - 0x2f */ \ |
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"ll", "lwc1", "lwc2", "lwc3", "lld", "ldc1", "ldc2", "ld", /* 0x30 - 0x37 */ \ |
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"sc", "swc1", "swc2", "swc3", "scd", "sdc1", "sdc2", "sd" /* 0x38 - 0x3f */ } |
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|
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#define REGIMM_NAMES { \ |
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"bltz", "bgez", "bltzl", "bgezl", "regimm_04", "regimm_05", "regimm_06", "regimm_07", /* 0x00 - 0x07 */ \ |
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"tgei", "tgeiu", "tlti", "tltiu", "teqi", "regimm_0d", "tnei", "regimm_0f", /* 0x08 - 0x0f */ \ |
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"bltzal", "bgezal", "bltzall", "bgezall", "regimm_14", "regimm_15", "regimm_16", "regimm_17", /* 0x10 - 0x17 */ \ |
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"mtsab", "mtsah", "regimm_1a", "regimm_1b", "regimm_1c", "regimm_1d", "regimm_1e", "synci" /* 0x18 - 0x1f */ } |
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|
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#define SPECIAL_NAMES { \ |
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"sll", "special_01", "srl", "sra", "sllv", "special_05", "srlv", "srav", /* 0x00 - 0x07 */ \ |
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"jr", "jalr", "movz", "movn", "syscall","break", "special_0e", "sync", /* 0x08 - 0x0f */ \ |
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"mfhi", "mthi", "mflo", "mtlo", "dsllv", "special_15", "dsrlv", "dsrav", /* 0x10 - 0x17 */ \ |
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"mult", "multu", "div", "divu", "dmult", "dmultu", "ddiv", "ddivu", /* 0x18 - 0x1f */ \ |
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"add", "addu", "sub", "subu", "and", "or", "xor", "nor", /* 0x20 - 0x27 */ \ |
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"special_28","special_29","slt", "sltu", "dadd", "daddu", "dsub", "dsubu", /* 0x28 - 0x2f */ \ |
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"tge", "tgeu", "tlt", "tltu", "teq", "special_35", "tne", "special_37",/* 0x30 - 0x37 */ \ |
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"dsll", "special_39", "dsrl", "dsra", "dsll32", "special_3d", "dsrl32", "dsra32" /* 0x38 - 0x3f */ } |
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|
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/* SPECIAL opcodes, when the rotate bit is set: */ |
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#define SPECIAL_ROT_NAMES { \ |
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"rot_00", "rot_01", "ror", "rot_03", "rot_04", "rot_05", "rorv", "rot_07", /* 0x00 - 0x07 */ \ |
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"rot_08", "rot_09", "rot_0a", "rot_0b", "rot_0c", "rot_0d", "rot_0e", "rot_0f", /* 0x08 - 0x0f */ \ |
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"rot_10", "rot_11", "rot_12", "rot_13", "rot_14", "rot_15", "drorv", "rot_17", /* 0x10 - 0x17 */ \ |
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"rot_18", "rot_19", "rot_1a", "rot_1b", "rot_1c", "rot_1d", "rot_1e", "rot_1f", /* 0x18 - 0x1f */ \ |
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"rot_20", "rot_21", "rot_22", "rot_23", "rot_24", "rot_25", "rot_26", "rot_27", /* 0x20 - 0x27 */ \ |
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"rot_28", "rot_29", "rot_2a", "rot_2b", "rot_2c", "rot_2d", "rot_2e", "rot_2f", /* 0x28 - 0x2f */ \ |
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"rot_30", "rot_31", "rot_32", "rot_33", "rot_34", "rot_35", "rot_36", "rot_37", /* 0x30 - 0x37 */ \ |
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"rot_38", "rot_39", "dror", "rot_3b", "rot_3c", "rot_3d", "dror32", "rot_3f" /* 0x38 - 0x3f */ } |
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|
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#define SPECIAL2_NAMES { \ |
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"madd", "maddu", "mul", "special2_03", "msub", "msubu", "special2_06", "special2_07", /* 0x00 - 0x07 */ \ |
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"special2_08", "special2_09", "special2_0a", "special2_0b", "special2_0c", "special2_0d", "special2_0e", "special2_0f", /* 0x08 - 0x0f */ \ |
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"special2_10", "special2_11", "special2_12", "special2_13", "special2_14", "special2_15", "special2_16", "special2_17", /* 0x10 - 0x17 */ \ |
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"special2_18", "special2_19", "special2_1a", "special2_1b", "special2_1c", "special2_1d", "special2_1e", "special2_1f", /* 0x18 - 0x1f */ \ |
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"clz", "clo", "special2_22", "special2_23", "dclz", "dclo", "special2_26", "special2_27", /* 0x20 - 0x27 */ \ |
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"special2_28", "special2_29", "special2_2a", "special2_2b", "special2_2c", "special2_2d", "special2_2e", "special2_2f", /* 0x28 - 0x2f */ \ |
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"special2_30", "special2_31", "special2_32", "special2_33", "special2_34", "special2_35", "special2_36", "special2_37", /* 0x30 - 0x37 */ \ |
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"special2_38", "special2_39", "special2_3a", "special2_3b", "special2_3c", "special2_3d", "special2_3e", "sdbbp" /* 0x38 - 0x3f */ } |
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|
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/* MMI (on R5900, TX79/C790) occupies the same space as SPECIAL2 */ |
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#define MMI_NAMES { \ |
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"madd", "maddu", "mmi_02", "mmi_03", "plzcw", "mmi_05", "mmi_06", "mmi_07", /* 0x00 - 0x07 */ \ |
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"mmi0", "mmi2", "mmi_0a", "mmi_0b", "mmi_0c", "mmi_0d", "mmi_0e", "mmi_0f", /* 0x08 - 0x0f */ \ |
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"mfhi1", "mthi1", "mflo1", "mtlo1", "mmi_14", "mmi_15", "mmi_16", "mmi_17", /* 0x10 - 0x17 */ \ |
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"mult1", "multu1", "div1", "divu1", "mmi_1c", "mmi_1d", "mmi_1e", "mmi_1f", /* 0x18 - 0x1f */ \ |
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"madd1", "maddu1", "mmi_22", "mmi_23", "mmi_24", "mmi_25", "mmi_26", "mmi_27", /* 0x20 - 0x27 */ \ |
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"mmi1", "mmi3", "mmi_2a", "mmi_2b", "mmi_2c", "mmi_2d", "mmi_2e", "mmi_2f", /* 0x28 - 0x2f */ \ |
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"pmfhl", "pmthl", "mmi_32", "mmi_33", "psllh", "mmi_35", "psrlh", "psrah", /* 0x30 - 0x37 */ \ |
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"mmi_38", "mmi_39", "mmi_3a", "mmi_3b", "psllw", "mmi_3d", "psrlw", "psraw" /* 0x38 - 0x3f */ } |
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|
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#define MMI0_NAMES { \ |
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"paddw", "psubw", "pcgtw", "pmaxw", /* 0x00 - 0x03 */ \ |
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"paddh", "psubh", "pcgth", "pmaxh", /* 0x04 - 0x07 */ \ |
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"paddb", "psubb", "pcgtb", "mmi0_0b", /* 0x08 - 0x0b */ \ |
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"mmi0_0c", "mmi0_0d", "mmi0_0e", "mmi0_0f", /* 0x0c - 0x0f */ \ |
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"paddsw", "psubsw", "pextlw", "ppacw", /* 0x10 - 0x13 */ \ |
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"paddsh", "psubsh", "pextlh", "ppach", /* 0x14 - 0x17 */ \ |
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"paddsb", "psubsb", "pextlb", "ppacb", /* 0x18 - 0x1b */ \ |
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"mmi0_1c", "mmi0_1d", "pext5", "ppac5" /* 0x1c - 0x1f */ } |
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|
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#define MMI1_NAMES { \ |
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"mmi1_00", "pabsw", "pceqw", "pminw", /* 0x00 - 0x03 */ \ |
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"padsbh", "pabsh", "pceqh", "pminh", /* 0x04 - 0x07 */ \ |
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"mmi1_08", "mmi1_09", "pceqb", "mmi1_0b", /* 0x08 - 0x0b */ \ |
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"mmi1_0c", "mmi1_0d", "mmi1_0e", "mmi1_0f", /* 0x0c - 0x0f */ \ |
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"padduw", "psubuw", "pextuw", "mmi1_13", /* 0x10 - 0x13 */ \ |
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"padduh", "psubuh", "pextuh", "mmi1_17", /* 0x14 - 0x17 */ \ |
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"paddub", "psubub", "pextub", "qfsrv", /* 0x18 - 0x1b */ \ |
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"mmi1_1c", "mmi1_1d", "mmi1_1e", "mmi1_1f" /* 0x1c - 0x1f */ } |
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|
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#define MMI2_NAMES { \ |
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"pmaddw", "mmi2_01", "psllvw", "psrlvw", /* 0x00 - 0x03 */ \ |
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"pmsubw", "mmi2_05", "mmi2_06", "mmi2_07", /* 0x04 - 0x07 */ \ |
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"pmfhi", "pmflo", "pinth", "mmi2_0b", /* 0x08 - 0x0b */ \ |
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"pmultw", "pdivw", "pcpyld" , "mmi2_0f", /* 0x0c - 0x0f */ \ |
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"pmaddh", "phmadh", "pand", "pxor", /* 0x10 - 0x13 */ \ |
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"pmsubh", "phmsbh", "mmi2_16", "mmi2_17", /* 0x14 - 0x17 */ \ |
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"mmi2_18", "mmi2_19", "pexeh", "prevh", /* 0x18 - 0x1b */ \ |
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"pmulth", "pdivbw", "pexew", "prot3w" /* 0x1c - 0x1f */ } |
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|
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#define MMI3_NAMES { \ |
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"pmadduw", "mmi3_01", "mmi3_02", "psravw", /* 0x00 - 0x03 */ \ |
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"mmi3_04", "mmi3_05", "mmi3_06", "mmi3_07", /* 0x04 - 0x07 */ \ |
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"pmthi", "pmtlo", "pinteh", "mmi3_0b", /* 0x08 - 0x0b */ \ |
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"pmultuw", "pdivuw", "pcpyud" , "mmi3_0f", /* 0x0c - 0x0f */ \ |
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"mmi3_10", "mmi3_11", "por", "pnor", /* 0x10 - 0x13 */ \ |
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"mmi3_14", "mmi3_15", "mmi3_16", "mmi3_17", /* 0x14 - 0x17 */ \ |
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"mmi3_18", "mmi3_19", "pexch", "pcpyh", /* 0x18 - 0x1b */ \ |
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"mmi3_1c", "mmi3_1d", "pexcw", "mmi3_1f" /* 0x1c - 0x1f */ } |
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|
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#define SPECIAL3_NAMES { \ |
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"ext", "dextm", "dextu", "dext", "ins", "dinsm", "dinsu", "dins", /* 0x00 - 0x07 */ \ |
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"special3_08", "special3_09", "special3_0a", "special3_0b", "special3_0c", "special3_0d", "special3_0e", "special3_0f", /* 0x08 - 0x0f */ \ |
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"special3_10", "special3_11", "special3_12", "special3_13", "special3_14", "special3_15", "special3_16", "special3_17", /* 0x10 - 0x17 */ \ |
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"special3_18", "special3_19", "special3_1a", "special3_1b", "special3_1c", "special3_1d", "special3_1e", "special3_1f", /* 0x18 - 0x1f */ \ |
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"bshfl", "special3_21", "special3_22", "special3_23", "dbshfl", "special3_25", "special3_26", "special3_27", /* 0x20 - 0x27 */ \ |
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"special3_28", "special3_29", "special3_2a", "special3_2b", "special3_2c", "special3_2d", "special3_2e", "special3_2f", /* 0x28 - 0x2f */ \ |
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"special3_30", "special3_31", "special3_32", "special3_33", "special3_34", "special3_35", "special3_36", "special3_37", /* 0x30 - 0x37 */ \ |
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"special3_38", "special3_39", "special3_3a", "rdhwr", "special3_3c", "special3_3d", "special3_3e", "special3_3f" /* 0x38 - 0x3f */ } |
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|
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#define HI6_SPECIAL 0x00 /* 000000 */ |
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#define SPECIAL_SLL 0x00 /* 000000 */ /* MIPS I */ |
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/* 0x01 000001 */ |
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#define SPECIAL_SRL 0x02 /* 000010 */ /* MIPS I */ |
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#define SPECIAL_SRA 0x03 /* 000011 */ /* MIPS I */ |
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#define SPECIAL_SLLV 0x04 /* 000100 */ /* MIPS I */ |
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/* 0x05 000101 */ |
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#define SPECIAL_SRLV 0x06 /* 000110 */ |
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#define SPECIAL_SRAV 0x07 /* 000111 */ /* MIPS I */ |
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#define SPECIAL_JR 0x08 /* 001000 */ /* MIPS I */ |
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#define SPECIAL_JALR 0x09 /* 001001 */ /* MIPS I */ |
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#define SPECIAL_MOVZ 0x0a /* 001010 */ /* MIPS IV */ |
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#define SPECIAL_MOVN 0x0b /* 001011 */ /* MIPS IV */ |
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#define SPECIAL_SYSCALL 0x0c /* 001100 */ /* MIPS I */ |
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#define SPECIAL_BREAK 0x0d /* 001101 */ /* MIPS I */ |
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/* 0x0e 001110 */ |
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#define SPECIAL_SYNC 0x0f /* 001111 */ /* MIPS II */ |
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#define SPECIAL_MFHI 0x10 /* 010000 */ /* MIPS I */ |
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#define SPECIAL_MTHI 0x11 /* 010001 */ /* MIPS I */ |
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#define SPECIAL_MFLO 0x12 /* 010010 */ /* MIPS I */ |
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#define SPECIAL_MTLO 0x13 /* 010011 */ /* MIPS I */ |
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#define SPECIAL_DSLLV 0x14 /* 010100 */ |
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/* 0x15 010101 */ |
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#define SPECIAL_DSRLV 0x16 /* 010110 */ /* MIPS III */ |
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#define SPECIAL_DSRAV 0x17 /* 010111 */ /* MIPS III */ |
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#define SPECIAL_MULT 0x18 /* 011000 */ /* MIPS I */ |
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#define SPECIAL_MULTU 0x19 /* 011001 */ /* MIPS I */ |
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#define SPECIAL_DIV 0x1a /* 011010 */ /* MIPS I */ |
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#define SPECIAL_DIVU 0x1b /* 011011 */ /* MIPS I */ |
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#define SPECIAL_DMULT 0x1c /* 011100 */ /* MIPS III */ |
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#define SPECIAL_DMULTU 0x1d /* 011101 */ /* MIPS III */ |
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#define SPECIAL_DDIV 0x1e /* 011110 */ /* MIPS III */ |
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#define SPECIAL_DDIVU 0x1f /* 011111 */ /* MIPS III */ |
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#define SPECIAL_ADD 0x20 /* 100000 */ /* MIPS I */ |
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#define SPECIAL_ADDU 0x21 /* 100001 */ /* MIPS I */ |
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#define SPECIAL_SUB 0x22 /* 100010 */ /* MIPS I */ |
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#define SPECIAL_SUBU 0x23 /* 100011 */ /* MIPS I */ |
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#define SPECIAL_AND 0x24 /* 100100 */ /* MIPS I */ |
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#define SPECIAL_OR 0x25 /* 100101 */ /* MIPS I */ |
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#define SPECIAL_XOR 0x26 /* 100110 */ /* MIPS I */ |
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#define SPECIAL_NOR 0x27 /* 100111 */ /* MIPS I */ |
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#define SPECIAL_MFSA 0x28 /* 101000 */ /* R5900/TX79/C790 */ |
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#define SPECIAL_MTSA 0x29 /* 101001 */ /* R5900/TX79/C790 */ |
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#define SPECIAL_SLT 0x2a /* 101010 */ /* MIPS I */ |
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#define SPECIAL_SLTU 0x2b /* 101011 */ /* MIPS I */ |
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#define SPECIAL_DADD 0x2c /* 101100 */ /* MIPS III */ |
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#define SPECIAL_DADDU 0x2d /* 101101 */ /* MIPS III */ |
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#define SPECIAL_DSUB 0x2e /* 101110 */ |
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#define SPECIAL_DSUBU 0x2f /* 101111 */ /* MIPS III */ |
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#define SPECIAL_TGE 0x30 /* 110000 */ |
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#define SPECIAL_TGEU 0x31 /* 110001 */ |
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#define SPECIAL_TLT 0x32 /* 110010 */ |
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#define SPECIAL_TLTU 0x33 /* 110011 */ |
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#define SPECIAL_TEQ 0x34 /* 110100 */ |
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/* 0x35 110101 */ |
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#define SPECIAL_TNE 0x36 /* 110110 */ |
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/* 0x37 110111 */ |
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#define SPECIAL_DSLL 0x38 /* 111000 */ /* MIPS III */ |
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/* 0x39 111001 */ |
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#define SPECIAL_DSRL 0x3a /* 111010 */ /* MIPS III */ |
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#define SPECIAL_DSRA 0x3b /* 111011 */ /* MIPS III */ |
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#define SPECIAL_DSLL32 0x3c /* 111100 */ /* MIPS III */ |
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/* 0x3d 111101 */ |
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#define SPECIAL_DSRL32 0x3e /* 111110 */ /* MIPS III */ |
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#define SPECIAL_DSRA32 0x3f /* 111111 */ /* MIPS III */ |
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|
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#define HI6_REGIMM 0x01 /* 000001 */ |
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#define REGIMM_BLTZ 0x00 /* 00000 */ /* MIPS I */ |
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#define REGIMM_BGEZ 0x01 /* 00001 */ /* MIPS I */ |
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#define REGIMM_BLTZL 0x02 /* 00010 */ /* MIPS II */ |
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#define REGIMM_BGEZL 0x03 /* 00011 */ /* MIPS II */ |
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#define REGIMM_TGEI 0x08 /* 01000 */ |
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#define REGIMM_TGEIU 0x09 /* 01001 */ |
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#define REGIMM_TLTI 0x0a /* 01010 */ |
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#define REGIMM_TLTIU 0x0b /* 01011 */ |
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#define REGIMM_TEQI 0x0c /* 01100 */ |
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#define REGIMM_TNEI 0x0e /* 01110 */ |
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#define REGIMM_BLTZAL 0x10 /* 10000 */ |
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#define REGIMM_BGEZAL 0x11 /* 10001 */ |
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#define REGIMM_BLTZALL 0x12 /* 10010 */ |
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#define REGIMM_BGEZALL 0x13 /* 10011 */ |
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#define REGIMM_MTSAB 0x18 /* 11000 */ /* R5900/TX79/C790 */ |
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#define REGIMM_MTSAH 0x19 /* 11001 */ /* R5900/TX79/C790 */ |
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#define REGIMM_SYNCI 0x1f /* 11111 */ |
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/* regimm ............... */ |
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|
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#define HI6_J 0x02 /* 000010 */ /* MIPS I */ |
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#define HI6_JAL 0x03 /* 000011 */ /* MIPS I */ |
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#define HI6_BEQ 0x04 /* 000100 */ /* MIPS I */ |
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#define HI6_BNE 0x05 /* 000101 */ |
| 260 |
#define HI6_BLEZ 0x06 /* 000110 */ /* MIPS I */ |
| 261 |
#define HI6_BGTZ 0x07 /* 000111 */ /* MIPS I */ |
| 262 |
#define HI6_ADDI 0x08 /* 001000 */ /* MIPS I */ |
| 263 |
#define HI6_ADDIU 0x09 /* 001001 */ /* MIPS I */ |
| 264 |
#define HI6_SLTI 0x0a /* 001010 */ /* MIPS I */ |
| 265 |
#define HI6_SLTIU 0x0b /* 001011 */ /* MIPS I */ |
| 266 |
#define HI6_ANDI 0x0c /* 001100 */ /* MIPS I */ |
| 267 |
#define HI6_ORI 0x0d /* 001101 */ /* MIPS I */ |
| 268 |
#define HI6_XORI 0x0e /* 001110 */ /* MIPS I */ |
| 269 |
#define HI6_LUI 0x0f /* 001111 */ /* MIPS I */ |
| 270 |
#define HI6_COP0 0x10 /* 010000 */ |
| 271 |
#define COPz_MFCz 0x00 /* 00000 */ |
| 272 |
#define COPz_DMFCz 0x01 /* 00001 */ |
| 273 |
#define COPz_MTCz 0x04 /* 00100 */ |
| 274 |
#define COPz_DMTCz 0x05 /* 00101 */ |
| 275 |
/* |
| 276 |
* For cop1 (the floating point coprocessor), if bits 25..21 are |
| 277 |
* a valid format, then bits 5..0 are the math opcode. |
| 278 |
* |
| 279 |
* Otherwise, bits 25..21 are the main coprocessor opcode. |
| 280 |
*/ |
| 281 |
#define COPz_CFCz 0x02 /* 00010 */ /* MIPS I */ |
| 282 |
#define COPz_CTCz 0x06 /* 00110 */ /* MIPS I */ |
| 283 |
#define COPz_BCzc 0x08 /* 01000 */ |
| 284 |
#define COPz_MFMCz 0x0b /* 01011 */ |
| 285 |
#define COP1_FMT_S 0x10 /* 10000 */ |
| 286 |
#define COP1_FMT_D 0x11 /* 10001 */ |
| 287 |
#define COP1_FMT_W 0x14 /* 10100 */ |
| 288 |
#define COP1_FMT_L 0x15 /* 10101 */ |
| 289 |
#define COP1_FMT_PS 0x16 /* 10110 */ |
| 290 |
/* COP0 opcodes = bits 7..0 (only if COP0 and CO=1): */ |
| 291 |
#define COP0_TLBR 0x01 /* 000001 */ |
| 292 |
#define COP0_TLBWI 0x02 /* 000010 */ |
| 293 |
#define COP0_TLBWR 0x06 /* 000110 */ |
| 294 |
#define COP0_TLBP 0x08 /* 001000 */ |
| 295 |
#define COP0_RFE 0x10 /* 010000 */ |
| 296 |
#define COP0_ERET 0x18 /* 011000 */ |
| 297 |
#define COP0_DERET 0x1f /* 011111 */ /* EJTAG */ |
| 298 |
#define COP0_WAIT 0x20 /* 100000 */ /* MIPS32/64 */ |
| 299 |
#define COP0_STANDBY 0x21 /* 100001 */ |
| 300 |
#define COP0_SUSPEND 0x22 /* 100010 */ |
| 301 |
#define COP0_HIBERNATE 0x23 /* 100011 */ |
| 302 |
#define COP0_EI 0x38 /* 111000 */ /* R5900/TX79/C790 */ |
| 303 |
#define COP0_DI 0x39 /* 111001 */ /* R5900/TX79/C790 */ |
| 304 |
#define HI6_COP1 0x11 /* 010001 */ |
| 305 |
#define HI6_COP2 0x12 /* 010010 */ |
| 306 |
#define HI6_COP3 0x13 /* 010011 */ |
| 307 |
#define HI6_BEQL 0x14 /* 010100 */ /* MIPS II */ |
| 308 |
#define HI6_BNEL 0x15 /* 010101 */ |
| 309 |
#define HI6_BLEZL 0x16 /* 010110 */ /* MIPS II */ |
| 310 |
#define HI6_BGTZL 0x17 /* 010111 */ /* MIPS II */ |
| 311 |
#define HI6_DADDI 0x18 /* 011000 */ /* MIPS III */ |
| 312 |
#define HI6_DADDIU 0x19 /* 011001 */ /* MIPS III */ |
| 313 |
#define HI6_LDL 0x1a /* 011010 */ /* MIPS III */ |
| 314 |
#define HI6_LDR 0x1b /* 011011 */ /* MIPS III */ |
| 315 |
#define HI6_SPECIAL2 0x1c /* 011100 */ |
| 316 |
#define SPECIAL2_MADD 0x00 /* 000000 */ /* MIPS32 (?) TODO */ |
| 317 |
#define SPECIAL2_MADDU 0x01 /* 000001 */ /* MIPS32 (?) TODO */ |
| 318 |
#define SPECIAL2_MUL 0x02 /* 000010 */ /* MIPS32 (?) TODO */ |
| 319 |
#define SPECIAL2_MSUB 0x04 /* 000100 */ /* MIPS32 (?) TODO */ |
| 320 |
#define SPECIAL2_MSUBU 0x05 /* 000001 */ /* MIPS32 (?) TODO */ |
| 321 |
#define SPECIAL2_CLZ 0x20 /* 100100 */ /* MIPS32 */ |
| 322 |
#define SPECIAL2_CLO 0x21 /* 100101 */ /* MIPS32 */ |
| 323 |
#define SPECIAL2_DCLZ 0x24 /* 100100 */ /* MIPS64 */ |
| 324 |
#define SPECIAL2_DCLO 0x25 /* 100101 */ /* MIPS64 */ |
| 325 |
#define SPECIAL2_SDBBP 0x3f /* 111111 */ /* EJTAG (?) TODO */ |
| 326 |
/* MMI (R5900, TX79/C790) occupies the same opcode space as SPECIAL2: */ |
| 327 |
#define MMI_MADD 0x00 |
| 328 |
#define MMI_MADDU 0x01 |
| 329 |
#define MMI_PLZCW 0x04 |
| 330 |
#define MMI_MMI0 0x08 |
| 331 |
#define MMI0_PADDW 0x00 |
| 332 |
#define MMI0_PSUBW 0x01 |
| 333 |
#define MMI0_PCGTW 0x02 |
| 334 |
#define MMI0_PMAXW 0x03 |
| 335 |
#define MMI0_PADDH 0x04 |
| 336 |
#define MMI0_PSUBH 0x05 |
| 337 |
#define MMI0_PCGTH 0x06 |
| 338 |
#define MMI0_PMAXH 0x07 |
| 339 |
#define MMI0_PADDB 0x08 |
| 340 |
#define MMI0_PSUBB 0x09 |
| 341 |
#define MMI0_PCGTB 0x0a |
| 342 |
#define MMI0_PADDSW 0x10 |
| 343 |
#define MMI0_PSUBSW 0x11 |
| 344 |
#define MMI0_PEXTLW 0x12 |
| 345 |
#define MMI0_PPACW 0x13 |
| 346 |
#define MMI0_PADDSH 0x14 |
| 347 |
#define MMI0_PSUBSH 0x15 |
| 348 |
#define MMI0_PEXTLH 0x16 |
| 349 |
#define MMI0_PPACH 0x17 |
| 350 |
#define MMI0_PADDSB 0x18 |
| 351 |
#define MMI0_PSUBSB 0x19 |
| 352 |
#define MMI0_PEXTLB 0x1a |
| 353 |
#define MMI0_PPACB 0x1b |
| 354 |
#define MMI0_PEXT5 0x1e |
| 355 |
#define MMI0_PPAC5 0x1f |
| 356 |
#define MMI_MMI2 0x09 |
| 357 |
#define MMI2_PMADDW 0x00 |
| 358 |
#define MMI2_PSLLVW 0x02 |
| 359 |
#define MMI2_PSRLVW 0x03 |
| 360 |
#define MMI2_PMSUBW 0x04 |
| 361 |
#define MMI2_PMFHI 0x08 |
| 362 |
#define MMI2_PMFLO 0x09 |
| 363 |
#define MMI2_PINTH 0x0a |
| 364 |
#define MMI2_PMULTW 0x0c |
| 365 |
#define MMI2_PDIVW 0x0d |
| 366 |
#define MMI2_PCPYLD 0x0e |
| 367 |
#define MMI2_PMADDH 0x10 |
| 368 |
#define MMI2_PHMADH 0x11 |
| 369 |
#define MMI2_PAND 0x12 |
| 370 |
#define MMI2_PXOR 0x13 |
| 371 |
#define MMI2_PMSUBH 0x14 |
| 372 |
#define MMI2_PHMSBH 0x15 |
| 373 |
#define MMI2_PEXEH 0x1a |
| 374 |
#define MMI2_PREVH 0x1b |
| 375 |
#define MMI2_PMULTH 0x1c |
| 376 |
#define MMI2_PDIVBW 0x1d |
| 377 |
#define MMI2_PEXEW 0x1e |
| 378 |
#define MMI2_PROT3W 0x1f |
| 379 |
#define MMI_MFHI1 0x10 |
| 380 |
#define MMI_MTHI1 0x11 |
| 381 |
#define MMI_MFLO1 0x12 |
| 382 |
#define MMI_MTLO1 0x13 |
| 383 |
#define MMI_MULT1 0x18 |
| 384 |
#define MMI_MULTU1 0x19 |
| 385 |
#define MMI_DIV1 0x1a |
| 386 |
#define MMI_DIVU1 0x1b |
| 387 |
#define MMI_MADD1 0x20 |
| 388 |
#define MMI_MADDU1 0x21 |
| 389 |
#define MMI_MMI1 0x28 |
| 390 |
#define MMI1_PABSW 0x01 |
| 391 |
#define MMI1_PCEQW 0x02 |
| 392 |
#define MMI1_PMINW 0x03 |
| 393 |
#define MMI1_PADSBH 0x04 |
| 394 |
#define MMI1_PABSH 0x05 |
| 395 |
#define MMI1_PCEQH 0x06 |
| 396 |
#define MMI1_PMINH 0x07 |
| 397 |
#define MMI1_PCEQB 0x0a |
| 398 |
#define MMI1_PADDUW 0x10 |
| 399 |
#define MMI1_PSUBUW 0x11 |
| 400 |
#define MMI1_PEXTUW 0x12 |
| 401 |
#define MMI1_PADDUH 0x14 |
| 402 |
#define MMI1_PSUBUH 0x15 |
| 403 |
#define MMI1_PEXTUH 0x16 |
| 404 |
#define MMI1_PADDUB 0x18 |
| 405 |
#define MMI1_PSUBUB 0x19 |
| 406 |
#define MMI1_PEXTUB 0x1a |
| 407 |
#define MMI1_QFSRV 0x1b |
| 408 |
#define MMI_MMI3 0x29 |
| 409 |
#define MMI3_PMADDUW 0x00 |
| 410 |
#define MMI3_PSRAVW 0x03 |
| 411 |
#define MMI3_PMTHI 0x08 |
| 412 |
#define MMI3_PMTLO 0x09 |
| 413 |
#define MMI3_PINTEH 0x0a |
| 414 |
#define MMI3_PMULTUW 0x0c |
| 415 |
#define MMI3_PDIVUW 0x0d |
| 416 |
#define MMI3_PCPYUD 0x0e |
| 417 |
#define MMI3_POR 0x12 |
| 418 |
#define MMI3_PNOR 0x13 |
| 419 |
#define MMI3_PEXCH 0x1a |
| 420 |
#define MMI3_PCPYH 0x1b |
| 421 |
#define MMI3_PEXCW 0x1e |
| 422 |
#define MMI_PMFHL 0x30 |
| 423 |
#define MMI_PMTHL 0x31 |
| 424 |
#define MMI_PSLLH 0x34 |
| 425 |
#define MMI_PSRLH 0x36 |
| 426 |
#define MMI_PSRAH 0x37 |
| 427 |
#define MMI_PSLLW 0x3c |
| 428 |
#define MMI_PSRLW 0x3e |
| 429 |
#define MMI_PSRAW 0x3f |
| 430 |
/* JALX (TODO) 0x1d 011101 */ |
| 431 |
#define HI6_LQ_MDMX 0x1e /* 011110 */ /* lq on R5900, MDMX on others? */ |
| 432 |
/* TODO: MDMX opcodes */ |
| 433 |
#define HI6_SQ_SPECIAL3 0x1f /* 011111 */ /* sq on R5900, SPECIAL3 on MIPS32/64 rev 2 */ |
| 434 |
#define SPECIAL3_EXT 0x00 /* 000000 */ |
| 435 |
#define SPECIAL3_DEXTM 0x01 /* 000001 */ |
| 436 |
#define SPECIAL3_DEXTU 0x02 /* 000010 */ |
| 437 |
#define SPECIAL3_DEXT 0x03 /* 000011 */ |
| 438 |
#define SPECIAL3_INS 0x04 /* 000100 */ |
| 439 |
#define SPECIAL3_DINSM 0x05 /* 000101 */ |
| 440 |
#define SPECIAL3_DINSU 0x06 /* 000110 */ |
| 441 |
#define SPECIAL3_DINS 0x07 /* 000111 */ |
| 442 |
#define SPECIAL3_BSHFL 0x20 /* 100000 */ |
| 443 |
#define BSHFL_WSBH 0x002 /* 00000..00010 */ |
| 444 |
#define BSHFL_SEB 0x010 /* 00000..10000 */ |
| 445 |
#define BSHFL_SEH 0x018 /* 00000..11000 */ |
| 446 |
#define SPECIAL3_DBSHFL 0x24 /* 100100 */ |
| 447 |
#define BSHFL_DSBH 0x002 /* 00000..00010 */ |
| 448 |
#define BSHFL_DSHD 0x005 /* 00000..00101 */ |
| 449 |
#define SPECIAL3_RDHWR 0x3b /* 111011 */ |
| 450 |
#define HI6_LB 0x20 /* 100000 */ /* MIPS I */ |
| 451 |
#define HI6_LH 0x21 /* 100001 */ /* MIPS I */ |
| 452 |
#define HI6_LWL 0x22 /* 100010 */ /* MIPS I */ |
| 453 |
#define HI6_LW 0x23 /* 100011 */ /* MIPS I */ |
| 454 |
#define HI6_LBU 0x24 /* 100100 */ /* MIPS I */ |
| 455 |
#define HI6_LHU 0x25 /* 100101 */ /* MIPS I */ |
| 456 |
#define HI6_LWR 0x26 /* 100110 */ /* MIPS I */ |
| 457 |
#define HI6_LWU 0x27 /* 100111 */ /* MIPS III */ |
| 458 |
#define HI6_SB 0x28 /* 101000 */ /* MIPS I */ |
| 459 |
#define HI6_SH 0x29 /* 101001 */ /* MIPS I */ |
| 460 |
#define HI6_SWL 0x2a /* 101010 */ /* MIPS I */ |
| 461 |
#define HI6_SW 0x2b /* 101011 */ /* MIPS I */ |
| 462 |
#define HI6_SDL 0x2c /* 101100 */ /* MIPS III */ |
| 463 |
#define HI6_SDR 0x2d /* 101101 */ /* MIPS III */ |
| 464 |
#define HI6_SWR 0x2e /* 101110 */ /* MIPS I */ |
| 465 |
#define HI6_CACHE 0x2f /* 101111 */ /* ??? R4000 */ |
| 466 |
#define HI6_LL 0x30 /* 110000 */ /* MIPS II */ |
| 467 |
#define HI6_LWC1 0x31 /* 110001 */ /* MIPS I */ |
| 468 |
#define HI6_LWC2 0x32 /* 110010 */ /* MIPS I */ |
| 469 |
#define HI6_LWC3 0x33 /* 110011 */ /* MIPS I */ |
| 470 |
#define HI6_LLD 0x34 /* 110100 */ /* MIPS III */ |
| 471 |
#define HI6_LDC1 0x35 /* 110101 */ /* MIPS II */ |
| 472 |
#define HI6_LDC2 0x36 /* 110110 */ /* MIPS II */ |
| 473 |
#define HI6_LD 0x37 /* 110111 */ /* MIPS III */ |
| 474 |
#define HI6_SC 0x38 /* 111000 */ /* MIPS II */ |
| 475 |
#define HI6_SWC1 0x39 /* 111001 */ /* MIPS I */ |
| 476 |
#define HI6_SWC2 0x3a /* 111010 */ /* MIPS I */ |
| 477 |
#define HI6_SWC3 0x3b /* 111011 */ /* MIPS I */ |
| 478 |
#define HI6_SCD 0x3c /* 111100 */ /* MIPS III */ |
| 479 |
#define HI6_SDC1 0x3d /* 111101 */ /* MIPS II */ |
| 480 |
#define HI6_SDC2 0x3e /* 111110 */ /* MIPS II */ |
| 481 |
#define HI6_SD 0x3f /* 111111 */ /* MIPS III */ |
| 482 |
|
| 483 |
|
| 484 |
#endif /* OPCODES_MIPS_H */ |
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