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/* gxemul: $Id: mips_cpuregs.h,v 1.3 2007/02/10 13:31:21 debug Exp $ */ |
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/* $NetBSD: cpuregs.h,v 1.69 2005/12/20 21:06:43 tron Exp $ */ |
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|
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/* |
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* Copyright (c) 1992, 1993 |
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* The Regents of the University of California. All rights reserved. |
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* |
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* This code is derived from software contributed to Berkeley by |
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* Ralph Campbell and Rick Macklem. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. Neither the name of the University nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* @(#)machConst.h 8.1 (Berkeley) 6/10/93 |
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* |
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* machConst.h -- |
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* |
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* Machine dependent constants. |
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* |
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* Copyright (C) 1989 Digital Equipment Corporation. |
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* Permission to use, copy, modify, and distribute this software and |
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* its documentation for any purpose and without fee is hereby granted, |
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* provided that the above copyright notice appears in all copies. |
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* Digital Equipment Corporation makes no representations about the |
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* suitability of this software for any purpose. It is provided "as is" |
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* without express or implied warranty. |
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* |
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, |
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* v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) |
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, |
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* v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) |
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* from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, |
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* v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) |
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*/ |
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|
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#ifndef _MIPS_CPUREGS_H_ |
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#define _MIPS_CPUREGS_H_ |
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|
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/* #include <sys/cdefs.h> */ /* For __CONCAT() */ |
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|
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#if defined(_KERNEL_OPT) |
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#include "opt_cputype.h" |
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#endif |
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|
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/* |
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* Address space. |
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* 32-bit mips CPUS partition their 32-bit address space into four segments: |
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* |
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* kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped |
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* kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped |
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* kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped |
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* kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped |
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* |
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* mips1 physical memory is limited to 512Mbytes, which is |
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* doubly mapped in kseg0 (cached) and kseg1 (uncached.) |
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* Caching of mapped addresses is controlled by bits in the TLB entry. |
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*/ |
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|
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#define MIPS_KUSEG_START 0x0 |
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#define MIPS_KSEG0_START 0x80000000 |
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#define MIPS_KSEG1_START 0xa0000000 |
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#define MIPS_KSEG2_START 0xc0000000 |
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#define MIPS_MAX_MEM_ADDR 0xbe000000 |
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#define MIPS_RESERVED_ADDR 0xbfc80000 |
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|
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#define MIPS_PHYS_MASK 0x1fffffff |
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|
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#define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) |
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#define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START) |
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#define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK) |
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#define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START) |
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|
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/* Map virtual address to index in mips3 r4k virtually-indexed cache */ |
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#define MIPS3_VA_TO_CINDEX(x) \ |
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((unsigned)(x) & 0xffffff | MIPS_KSEG0_START) |
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|
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#define MIPS_PHYS_TO_XKPHYS(cca,x) \ |
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((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) |
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#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL) |
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|
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/* CPU dependent mtc0 hazard hook */ |
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#define COP0_SYNC /* nothing */ |
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#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; |
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|
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/* |
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* The bits in the cause register. |
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* |
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* Bits common to r3000 and r4000: |
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* |
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* MIPS_CR_BR_DELAY Exception happened in branch delay slot. |
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* MIPS_CR_COP_ERR Coprocessor error. |
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* MIPS_CR_IP Interrupt pending bits defined below. |
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* (same meaning as in CAUSE register). |
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* MIPS_CR_EXC_CODE The exception type (see exception codes below). |
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* |
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* Differences: |
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* r3k has 4 bits of execption type, r4k has 5 bits. |
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*/ |
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#define MIPS_CR_BR_DELAY 0x80000000 |
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#define MIPS_CR_COP_ERR 0x30000000 |
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#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ |
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#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ |
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#define MIPS_CR_IP 0x0000FF00 |
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#define MIPS_CR_EXC_CODE_SHIFT 2 |
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|
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/* |
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* The bits in the status register. All bits are active when set to 1. |
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* |
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* R3000 status register fields: |
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* MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. |
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* MIPS_SR_TS TLB shutdown. |
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* |
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* MIPS_SR_INT_IE Master (current) interrupt enable bit. |
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* |
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* Differences: |
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* r3k has cache control is via frobbing SR register bits, whereas the |
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* r4k cache control is via explicit instructions. |
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* r3k has a 3-entry stack of kernel/user bits, whereas the |
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* r4k has kernel/supervisor/user. |
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*/ |
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#define MIPS_SR_COP_USABILITY 0xf0000000 |
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#define MIPS_SR_COP_0_BIT 0x10000000 |
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#define MIPS_SR_COP_1_BIT 0x20000000 |
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|
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/* r4k and r3k differences, see below */ |
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|
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#define MIPS_SR_MX 0x01000000 /* MIPS64 */ |
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#define MIPS_SR_PX 0x00800000 /* MIPS64 */ |
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#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ |
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#define MIPS_SR_TS 0x00200000 |
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|
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/* r4k and r3k differences, see below */ |
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|
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#define MIPS_SR_INT_IE 0x00000001 |
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/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ |
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/*#define MIPS_SR_INT_MASK 0x0000ff00*/ |
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|
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|
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/* |
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* The R2000/R3000-specific status register bit definitions. |
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* all bits are active when set to 1. |
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* |
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* MIPS_SR_PARITY_ERR Parity error. |
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* MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. |
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* MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. |
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* MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. |
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* MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. |
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* Interrupt enable bits defined below. |
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* MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. |
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* MIPS_SR_INT_ENA_OLD Old interrupt enable bit. |
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* MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. |
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* MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. |
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* MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. |
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*/ |
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|
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#define MIPS1_PARITY_ERR 0x00100000 |
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#define MIPS1_CACHE_MISS 0x00080000 |
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#define MIPS1_PARITY_ZERO 0x00040000 |
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#define MIPS1_SWAP_CACHES 0x00020000 |
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#define MIPS1_ISOL_CACHES 0x00010000 |
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|
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#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ |
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#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ |
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#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ |
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#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ |
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#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ |
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|
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/* backwards compatibility */ |
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#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR |
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#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS |
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#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO |
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#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES |
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#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES |
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|
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#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD |
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#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD |
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#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV |
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#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR |
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#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV |
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|
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/* |
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* R4000 status register bit definitons, |
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* where different from r2000/r3000. |
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*/ |
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#define MIPS3_SR_XX 0x80000000 |
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#define MIPS3_SR_RP 0x08000000 |
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#define MIPS3_SR_FR 0x04000000 |
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#define MIPS3_SR_RE 0x02000000 |
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|
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#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ |
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#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ |
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#define MIPS3_SR_SR 0x00100000 |
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#define MIPS3_SR_EIE 0x00100000 /* TX79/R5900 */ |
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#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ |
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#define MIPS3_SR_DIAG_CH 0x00040000 |
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#define MIPS3_SR_DIAG_CE 0x00020000 |
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#define MIPS3_SR_DIAG_PE 0x00010000 |
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#define MIPS3_SR_KX 0x00000080 |
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#define MIPS3_SR_SX 0x00000040 |
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#define MIPS3_SR_UX 0x00000020 |
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#define MIPS3_SR_KSU_MASK 0x00000018 |
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#define MIPS3_SR_KSU_USER 0x00000010 |
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#define MIPS3_SR_KSU_SUPER 0x00000008 |
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#define MIPS3_SR_KSU_KERNEL 0x00000000 |
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#define MIPS3_SR_ERL 0x00000004 |
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#define MIPS3_SR_EXL 0x00000002 |
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|
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#ifdef MIPS3_5900 |
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#undef MIPS_SR_INT_IE |
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#define MIPS_SR_INT_IE 0x00010001 /* XXX */ |
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#endif |
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|
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#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET |
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#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH |
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#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE |
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#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE |
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#define MIPS_SR_KX MIPS3_SR_KX |
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#define MIPS_SR_SX MIPS3_SR_SX |
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#define MIPS_SR_UX MIPS3_SR_UX |
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|
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#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK |
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#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER |
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#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER |
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#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL |
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#define MIPS_SR_ERL MIPS3_SR_ERL |
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#define MIPS_SR_EXL MIPS3_SR_EXL |
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|
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|
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/* |
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* The interrupt masks. |
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* If a bit in the mask is 1 then the interrupt is enabled (or pending). |
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*/ |
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#define MIPS_INT_MASK 0xff00 |
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#define MIPS_INT_MASK_5 0x8000 |
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#define MIPS_INT_MASK_4 0x4000 |
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#define MIPS_INT_MASK_3 0x2000 |
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#define MIPS_INT_MASK_2 0x1000 |
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#define MIPS_INT_MASK_1 0x0800 |
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#define MIPS_INT_MASK_0 0x0400 |
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#define MIPS_HARD_INT_MASK 0xfc00 |
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#define MIPS_SOFT_INT_MASK_1 0x0200 |
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#define MIPS_SOFT_INT_MASK_0 0x0100 |
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|
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/* |
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* mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can |
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* choose to enable this interrupt. |
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*/ |
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#if defined(MIPS3_ENABLE_CLOCK_INTR) |
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#define MIPS3_INT_MASK MIPS_INT_MASK |
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#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK |
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#else |
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#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) |
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#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) |
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#endif |
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|
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/* |
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* The bits in the context register. |
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*/ |
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#define MIPS1_CNTXT_PTE_BASE 0xFFE00000 |
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#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC |
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|
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#define MIPS3_CNTXT_PTE_BASE 0xFF800000 |
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#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 |
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|
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/* |
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* The bits in the MIPS3 config register. |
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* |
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* bit 0..5: R/W, Bit 6..31: R/O |
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*/ |
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|
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/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ |
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#define MIPS3_CONFIG_K0_MASK 0x00000007 |
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|
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/* |
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* R/W Update on Store Conditional |
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* 0: Store Conditional uses coherency algorithm specified by TLB |
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* 1: Store Conditional uses cacheable coherent update on write |
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*/ |
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#define MIPS3_CONFIG_CU 0x00000008 |
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|
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#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ |
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#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ |
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#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ |
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(((config) & (bit)) ? 32 : 16) |
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|
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#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ |
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#define MIPS3_CONFIG_DC_SHIFT 6 |
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#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ |
| 310 |
#define MIPS3_CONFIG_IC_SHIFT 9 |
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#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ |
| 312 |
|
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/* Cache size mode indication: available only on Vr41xx CPUs */ |
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#define MIPS3_CONFIG_CS 0x00001000 |
| 315 |
#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ |
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#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ |
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((base) << (((config) & (mask)) >> (shift))) |
| 318 |
|
| 319 |
/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ |
| 320 |
#define MIPS3_CONFIG_SE 0x00001000 |
| 321 |
|
| 322 |
/* Block ordering: 0: sequential, 1: sub-block */ |
| 323 |
#define MIPS3_CONFIG_EB 0x00002000 |
| 324 |
|
| 325 |
/* ECC mode - 0: ECC mode, 1: parity mode */ |
| 326 |
#define MIPS3_CONFIG_EM 0x00004000 |
| 327 |
|
| 328 |
/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ |
| 329 |
#define MIPS3_CONFIG_BE 0x00008000 |
| 330 |
|
| 331 |
/* Dirty Shared coherency state - 0: enabled, 1: disabled */ |
| 332 |
#define MIPS3_CONFIG_SM 0x00010000 |
| 333 |
|
| 334 |
/* Secondary Cache - 0: present, 1: not present */ |
| 335 |
#define MIPS3_CONFIG_SC 0x00020000 |
| 336 |
|
| 337 |
/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ |
| 338 |
#define MIPS3_CONFIG_EW_MASK 0x000c0000 |
| 339 |
#define MIPS3_CONFIG_EW_SHIFT 18 |
| 340 |
|
| 341 |
/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ |
| 342 |
#define MIPS3_CONFIG_SW 0x00100000 |
| 343 |
|
| 344 |
/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ |
| 345 |
#define MIPS3_CONFIG_SS 0x00200000 |
| 346 |
|
| 347 |
/* Secondary Cache line size */ |
| 348 |
#define MIPS3_CONFIG_SB_MASK 0x00c00000 |
| 349 |
#define MIPS3_CONFIG_SB_SHIFT 22 |
| 350 |
#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ |
| 351 |
(0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) |
| 352 |
|
| 353 |
/* Write back data rate */ |
| 354 |
#define MIPS3_CONFIG_EP_MASK 0x0f000000 |
| 355 |
#define MIPS3_CONFIG_EP_SHIFT 24 |
| 356 |
|
| 357 |
/* System clock ratio - this value is CPU dependent */ |
| 358 |
#define MIPS3_CONFIG_EC_MASK 0x70000000 |
| 359 |
#define MIPS3_CONFIG_EC_SHIFT 28 |
| 360 |
|
| 361 |
/* Master-Checker Mode - 1: enabled */ |
| 362 |
#define MIPS3_CONFIG_CM 0x80000000 |
| 363 |
|
| 364 |
/* |
| 365 |
* The bits in the MIPS4 config register. |
| 366 |
*/ |
| 367 |
|
| 368 |
/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ |
| 369 |
#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK |
| 370 |
#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ |
| 371 |
#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ |
| 372 |
#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ |
| 373 |
#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ |
| 374 |
#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ |
| 375 |
#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ |
| 376 |
#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ |
| 377 |
#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ |
| 378 |
#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ |
| 379 |
#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ |
| 380 |
#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ |
| 381 |
#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ |
| 382 |
#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ |
| 383 |
|
| 384 |
#define MIPS4_CONFIG_DC_SHIFT 26 |
| 385 |
#define MIPS4_CONFIG_IC_SHIFT 29 |
| 386 |
|
| 387 |
#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ |
| 388 |
((base) << (((config) & (mask)) >> (shift))) |
| 389 |
|
| 390 |
#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ |
| 391 |
(((config) & MIPS4_CONFIG_SB) ? 128 : 64) |
| 392 |
|
| 393 |
/* |
| 394 |
* Location of exception vectors. |
| 395 |
* |
| 396 |
* Common vectors: reset and UTLB miss. |
| 397 |
*/ |
| 398 |
#define MIPS_RESET_EXC_VEC 0xBFC00000 |
| 399 |
#define MIPS_UTLB_MISS_EXC_VEC 0x80000000 |
| 400 |
|
| 401 |
/* |
| 402 |
* MIPS-1 general exception vector (everything else) |
| 403 |
*/ |
| 404 |
#define MIPS1_GEN_EXC_VEC 0x80000080 |
| 405 |
|
| 406 |
/* |
| 407 |
* MIPS-III exception vectors |
| 408 |
*/ |
| 409 |
#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 |
| 410 |
#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 |
| 411 |
#define MIPS3_GEN_EXC_VEC 0x80000180 |
| 412 |
|
| 413 |
/* |
| 414 |
* TX79 (R5900) exception vectors |
| 415 |
*/ |
| 416 |
#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 |
| 417 |
#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 |
| 418 |
|
| 419 |
/* |
| 420 |
* MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. |
| 421 |
*/ |
| 422 |
#define MIPS3_INTR_EXC_VEC 0x80000200 |
| 423 |
|
| 424 |
/* |
| 425 |
* Coprocessor 0 registers: |
| 426 |
* |
| 427 |
* v--- width for mips I,III,32,64 |
| 428 |
* (3=32bit, 6=64bit, i=impl dep) |
| 429 |
* 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. |
| 430 |
* 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. |
| 431 |
* 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low. |
| 432 |
* 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. |
| 433 |
* 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. |
| 434 |
* 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. |
| 435 |
* 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. |
| 436 |
* 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. |
| 437 |
* 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. |
| 438 |
* 9 MIPS_COP_0_COUNT .333 Count register. |
| 439 |
* 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. |
| 440 |
* 11 MIPS_COP_0_COMPARE .333 Compare (against Count). |
| 441 |
* 12 MIPS_COP_0_STATUS 3333 Status register. |
| 442 |
* 13 MIPS_COP_0_CAUSE 3333 Exception cause register. |
| 443 |
* 14 MIPS_COP_0_EXC_PC 3636 Exception PC. |
| 444 |
* 15 MIPS_COP_0_PRID 3333 Processor revision identifier. |
| 445 |
* 16 MIPS_COP_0_CONFIG 3333 Configuration register. |
| 446 |
* 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. |
| 447 |
* 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. |
| 448 |
* 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. |
| 449 |
* 17 MIPS_COP_0_LLADDR .336 Load Linked Address. |
| 450 |
* 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. |
| 451 |
* 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. |
| 452 |
* 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. |
| 453 |
* 23 MIPS_COP_0_DEBUG .... Debug JTAG register. |
| 454 |
* 24 MIPS_COP_0_DEPC .... DEPC JTAG register. |
| 455 |
* 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. |
| 456 |
* 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. |
| 457 |
* 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. |
| 458 |
* 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). |
| 459 |
* 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). |
| 460 |
* 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). |
| 461 |
* 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). |
| 462 |
* 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). |
| 463 |
* 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). |
| 464 |
* 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). |
| 465 |
* 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). |
| 466 |
* 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. |
| 467 |
* 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. |
| 468 |
*/ |
| 469 |
#ifdef _LOCORE |
| 470 |
#define _(n) __CONCAT($,n) |
| 471 |
#else |
| 472 |
#define _(n) n |
| 473 |
#endif |
| 474 |
#define MIPS_COP_0_TLB_INDEX _(0) |
| 475 |
#define MIPS_COP_0_TLB_RANDOM _(1) |
| 476 |
/* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ |
| 477 |
|
| 478 |
#define MIPS_COP_0_TLB_CONTEXT _(4) |
| 479 |
/* $5 and $6 new with MIPS-III */ |
| 480 |
#define MIPS_COP_0_BAD_VADDR _(8) |
| 481 |
#define MIPS_COP_0_TLB_HI _(10) |
| 482 |
#define MIPS_COP_0_STATUS _(12) |
| 483 |
#define MIPS_COP_0_CAUSE _(13) |
| 484 |
#define MIPS_COP_0_EXC_PC _(14) |
| 485 |
#define MIPS_COP_0_PRID _(15) |
| 486 |
|
| 487 |
|
| 488 |
/* MIPS-I */ |
| 489 |
#define MIPS_COP_0_TLB_LOW _(2) |
| 490 |
|
| 491 |
/* MIPS-III */ |
| 492 |
#define MIPS_COP_0_TLB_LO0 _(2) |
| 493 |
#define MIPS_COP_0_TLB_LO1 _(3) |
| 494 |
|
| 495 |
#define MIPS_COP_0_TLB_PG_MASK _(5) |
| 496 |
#define MIPS_COP_0_TLB_WIRED _(6) |
| 497 |
|
| 498 |
#define MIPS_COP_0_COUNT _(9) |
| 499 |
#define MIPS_COP_0_COMPARE _(11) |
| 500 |
|
| 501 |
#define MIPS_COP_0_CONFIG _(16) |
| 502 |
#define MIPS_COP_0_LLADDR _(17) |
| 503 |
#define MIPS_COP_0_WATCH_LO _(18) |
| 504 |
#define MIPS_COP_0_WATCH_HI _(19) |
| 505 |
#define MIPS_COP_0_TLB_XCONTEXT _(20) |
| 506 |
#define MIPS_COP_0_ECC _(26) |
| 507 |
#define MIPS_COP_0_CACHE_ERR _(27) |
| 508 |
#define MIPS_COP_0_TAG_LO _(28) |
| 509 |
#define MIPS_COP_0_TAG_HI _(29) |
| 510 |
#define MIPS_COP_0_ERROR_PC _(30) |
| 511 |
|
| 512 |
/* MIPS32/64 */ |
| 513 |
#define MIPS_COP_0_DEBUG _(23) |
| 514 |
#define MIPS_COP_0_DEPC _(24) |
| 515 |
#define MIPS_COP_0_PERFCNT _(25) |
| 516 |
#define MIPS_COP_0_DATA_LO _(28) |
| 517 |
#define MIPS_COP_0_DATA_HI _(29) |
| 518 |
#define MIPS_COP_0_DESAVE _(31) |
| 519 |
|
| 520 |
/* |
| 521 |
* Values for the code field in a break instruction. |
| 522 |
*/ |
| 523 |
#define MIPS_BREAK_INSTR 0x0000000d |
| 524 |
#define MIPS_BREAK_VAL_MASK 0x03ff0000 |
| 525 |
#define MIPS_BREAK_VAL_SHIFT 16 |
| 526 |
#define MIPS_BREAK_KDB_VAL 512 |
| 527 |
#define MIPS_BREAK_SSTEP_VAL 513 |
| 528 |
#define MIPS_BREAK_BRKPT_VAL 514 |
| 529 |
#define MIPS_BREAK_SOVER_VAL 515 |
| 530 |
#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ |
| 531 |
(MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) |
| 532 |
#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ |
| 533 |
(MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) |
| 534 |
#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ |
| 535 |
(MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) |
| 536 |
#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ |
| 537 |
(MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) |
| 538 |
|
| 539 |
/* |
| 540 |
* Mininum and maximum cache sizes. |
| 541 |
*/ |
| 542 |
#define MIPS_MIN_CACHE_SIZE (16 * 1024) |
| 543 |
#define MIPS_MAX_CACHE_SIZE (256 * 1024) |
| 544 |
#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ |
| 545 |
|
| 546 |
/* |
| 547 |
* The floating point version and status registers. |
| 548 |
*/ |
| 549 |
#define MIPS_FPU_ID $0 |
| 550 |
#define MIPS_FPU_CSR $31 |
| 551 |
|
| 552 |
/* |
| 553 |
* The floating point coprocessor status register bits. |
| 554 |
*/ |
| 555 |
#define MIPS_FPU_ROUNDING_BITS 0x00000003 |
| 556 |
#define MIPS_FPU_ROUND_RN 0x00000000 |
| 557 |
#define MIPS_FPU_ROUND_RZ 0x00000001 |
| 558 |
#define MIPS_FPU_ROUND_RP 0x00000002 |
| 559 |
#define MIPS_FPU_ROUND_RM 0x00000003 |
| 560 |
#define MIPS_FPU_STICKY_BITS 0x0000007c |
| 561 |
#define MIPS_FPU_STICKY_INEXACT 0x00000004 |
| 562 |
#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 |
| 563 |
#define MIPS_FPU_STICKY_OVERFLOW 0x00000010 |
| 564 |
#define MIPS_FPU_STICKY_DIV0 0x00000020 |
| 565 |
#define MIPS_FPU_STICKY_INVALID 0x00000040 |
| 566 |
#define MIPS_FPU_ENABLE_BITS 0x00000f80 |
| 567 |
#define MIPS_FPU_ENABLE_INEXACT 0x00000080 |
| 568 |
#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 |
| 569 |
#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 |
| 570 |
#define MIPS_FPU_ENABLE_DIV0 0x00000400 |
| 571 |
#define MIPS_FPU_ENABLE_INVALID 0x00000800 |
| 572 |
#define MIPS_FPU_EXCEPTION_BITS 0x0003f000 |
| 573 |
#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 |
| 574 |
#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 |
| 575 |
#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 |
| 576 |
#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 |
| 577 |
#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 |
| 578 |
#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 |
| 579 |
#define MIPS_FPU_COND_BIT 0x00800000 |
| 580 |
#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ |
| 581 |
#define MIPS1_FPC_MBZ_BITS 0xff7c0000 |
| 582 |
#define MIPS3_FPC_MBZ_BITS 0xfe7c0000 |
| 583 |
|
| 584 |
|
| 585 |
/* |
| 586 |
* Constants to determine if have a floating point instruction. |
| 587 |
*/ |
| 588 |
#define MIPS_OPCODE_SHIFT 26 |
| 589 |
#define MIPS_OPCODE_C1 0x11 |
| 590 |
|
| 591 |
|
| 592 |
/* |
| 593 |
* The low part of the TLB entry. |
| 594 |
*/ |
| 595 |
#define MIPS1_TLB_PFN 0xfffff000 |
| 596 |
#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 |
| 597 |
#define MIPS1_TLB_DIRTY_BIT 0x00000400 |
| 598 |
#define MIPS1_TLB_VALID_BIT 0x00000200 |
| 599 |
#define MIPS1_TLB_GLOBAL_BIT 0x00000100 |
| 600 |
|
| 601 |
#define MIPS3_TLB_PFN 0x3fffffc0 |
| 602 |
#define MIPS3_TLB_ATTR_MASK 0x00000038 |
| 603 |
#define MIPS3_TLB_ATTR_SHIFT 3 |
| 604 |
#define MIPS3_TLB_DIRTY_BIT 0x00000004 |
| 605 |
#define MIPS3_TLB_VALID_BIT 0x00000002 |
| 606 |
#define MIPS3_TLB_GLOBAL_BIT 0x00000001 |
| 607 |
|
| 608 |
#define MIPS1_TLB_PHYS_PAGE_SHIFT 12 |
| 609 |
#define MIPS3_TLB_PHYS_PAGE_SHIFT 6 |
| 610 |
#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN |
| 611 |
#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN |
| 612 |
#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT |
| 613 |
#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT |
| 614 |
|
| 615 |
/* |
| 616 |
* MIPS3_TLB_ATTR values - coherency algorithm: |
| 617 |
* 0: cacheable, noncoherent, write-through, no write allocate |
| 618 |
* 1: cacheable, noncoherent, write-through, write allocate |
| 619 |
* 2: uncached |
| 620 |
* 3: cacheable, noncoherent, write-back (noncoherent) |
| 621 |
* 4: cacheable, coherent, write-back, exclusive (exclusive) |
| 622 |
* 5: cacheable, coherent, write-back, exclusive on write (sharable) |
| 623 |
* 6: cacheable, coherent, write-back, update on write (update) |
| 624 |
* 7: uncached, accelerated (gather STORE operations) |
| 625 |
*/ |
| 626 |
#define MIPS3_TLB_ATTR_WT 0 /* IDT */ |
| 627 |
#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ |
| 628 |
#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ |
| 629 |
#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ |
| 630 |
#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ |
| 631 |
#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ |
| 632 |
#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ |
| 633 |
#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ |
| 634 |
|
| 635 |
|
| 636 |
/* |
| 637 |
* The high part of the TLB entry. |
| 638 |
*/ |
| 639 |
#define MIPS1_TLB_VPN 0xfffff000 |
| 640 |
#define MIPS1_TLB_PID 0x00000fc0 |
| 641 |
#define MIPS1_TLB_PID_SHIFT 6 |
| 642 |
|
| 643 |
#define MIPS3_TLB_VPN2 0xffffe000 |
| 644 |
#define MIPS3_TLB_ASID 0x000000ff |
| 645 |
|
| 646 |
#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN |
| 647 |
#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 |
| 648 |
#define MIPS3_TLB_PID MIPS3_TLB_ASID |
| 649 |
#define MIPS_TLB_VIRT_PAGE_SHIFT 12 |
| 650 |
|
| 651 |
/* |
| 652 |
* r3000: shift count to put the index in the right spot. |
| 653 |
*/ |
| 654 |
#define MIPS1_TLB_INDEX_SHIFT 8 |
| 655 |
|
| 656 |
/* |
| 657 |
* The first TLB that write random hits. |
| 658 |
*/ |
| 659 |
#define MIPS1_TLB_FIRST_RAND_ENTRY 8 |
| 660 |
#define MIPS3_TLB_WIRED_UPAGES 1 |
| 661 |
|
| 662 |
/* |
| 663 |
* The number of process id entries. |
| 664 |
*/ |
| 665 |
#define MIPS1_TLB_NUM_PIDS 64 |
| 666 |
#define MIPS3_TLB_NUM_ASIDS 256 |
| 667 |
|
| 668 |
/* |
| 669 |
* Patch codes to hide CPU design differences between MIPS1 and MIPS3. |
| 670 |
*/ |
| 671 |
|
| 672 |
/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ |
| 673 |
|
| 674 |
#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ |
| 675 |
&& defined(MIPS1) /* XXX simonb must be neater! */ |
| 676 |
#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT |
| 677 |
#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS |
| 678 |
#endif |
| 679 |
|
| 680 |
#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ |
| 681 |
&& !defined(MIPS1) /* XXX simonb must be neater! */ |
| 682 |
#define MIPS_TLB_PID_SHIFT 0 |
| 683 |
#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS |
| 684 |
#endif |
| 685 |
|
| 686 |
|
| 687 |
#if !defined(MIPS_TLB_PID_SHIFT) |
| 688 |
#define MIPS_TLB_PID_SHIFT \ |
| 689 |
((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) |
| 690 |
|
| 691 |
#define MIPS_TLB_NUM_PIDS \ |
| 692 |
((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) |
| 693 |
#endif |
| 694 |
|
| 695 |
/* |
| 696 |
* CPU processor revision IDs for company ID == 0 (non mips32/64 chips) |
| 697 |
*/ |
| 698 |
#define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ |
| 699 |
#define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ |
| 700 |
#define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ |
| 701 |
#define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ |
| 702 |
#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ |
| 703 |
#define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ |
| 704 |
#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ |
| 705 |
#define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ |
| 706 |
#define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ |
| 707 |
#define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ |
| 708 |
#define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ |
| 709 |
#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ |
| 710 |
#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ |
| 711 |
#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ |
| 712 |
#define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ |
| 713 |
#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ |
| 714 |
#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ |
| 715 |
#define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ |
| 716 |
#define MIPS_R4650 0x22 /* QED R4650 ISA III */ |
| 717 |
#define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ |
| 718 |
#define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ |
| 719 |
#define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ |
| 720 |
#define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ |
| 721 |
#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ |
| 722 |
#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ |
| 723 |
#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ |
| 724 |
#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ |
| 725 |
#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ |
| 726 |
#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ |
| 727 |
#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ |
| 728 |
#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ |
| 729 |
|
| 730 |
/* |
| 731 |
* CPU revision IDs for some prehistoric processors. |
| 732 |
*/ |
| 733 |
|
| 734 |
/* For MIPS_R3000 */ |
| 735 |
#define MIPS_REV_R3000 0x20 |
| 736 |
#define MIPS_REV_R3000A 0x30 |
| 737 |
|
| 738 |
/* For MIPS_TX3900 */ |
| 739 |
#define MIPS_REV_TX3912 0x10 |
| 740 |
#define MIPS_REV_TX3922 0x30 |
| 741 |
#define MIPS_REV_TX3927 0x40 |
| 742 |
|
| 743 |
/* For MIPS_R4000 */ |
| 744 |
#define MIPS_REV_R4000_A 0x00 |
| 745 |
#define MIPS_REV_R4000_B 0x22 |
| 746 |
#define MIPS_REV_R4000_C 0x30 |
| 747 |
#define MIPS_REV_R4400_A 0x40 |
| 748 |
#define MIPS_REV_R4400_B 0x50 |
| 749 |
#define MIPS_REV_R4400_C 0x60 |
| 750 |
|
| 751 |
/* For MIPS_TX4900 */ |
| 752 |
#define MIPS_REV_TX4927 0x22 |
| 753 |
|
| 754 |
/* |
| 755 |
* CPU processor revision IDs for company ID == 1 (MIPS) |
| 756 |
*/ |
| 757 |
#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ |
| 758 |
#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ |
| 759 |
#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ |
| 760 |
#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ |
| 761 |
#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ |
| 762 |
#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ |
| 763 |
#define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ |
| 764 |
#define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ |
| 765 |
#define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ |
| 766 |
#define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ |
| 767 |
#define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ |
| 768 |
#define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ |
| 769 |
#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ |
| 770 |
#define MIPS_24K 0x93 /* MIPS 24K ? */ |
| 771 |
#define MIPS_34K 0x95 /* MIPS 34K ? */ |
| 772 |
#define MIPS_24KE 0x96 /* MIPS 24KE ? */ |
| 773 |
#define MIPS_74K 0x97 /* MIPS 74K ? */ |
| 774 |
|
| 775 |
/* |
| 776 |
* Alchemy (company ID 3) use the processor ID field to donote the CPU core |
| 777 |
* revision and the company options field do donate the SOC chip type. |
| 778 |
*/ |
| 779 |
/* CPU processor revision IDs */ |
| 780 |
#define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ |
| 781 |
#define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ |
| 782 |
/* CPU company options IDs */ |
| 783 |
#define MIPS_AU1000 0x00 |
| 784 |
#define MIPS_AU1500 0x01 |
| 785 |
#define MIPS_AU1100 0x02 |
| 786 |
#define MIPS_AU1550 0x03 |
| 787 |
|
| 788 |
/* |
| 789 |
* CPU processor revision IDs for company ID == 4 (SiByte) |
| 790 |
*/ |
| 791 |
#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ |
| 792 |
|
| 793 |
/* |
| 794 |
* CPU processor revision IDs for company ID == 5 (SandCraft) |
| 795 |
*/ |
| 796 |
#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ |
| 797 |
|
| 798 |
/* |
| 799 |
* FPU processor revision ID |
| 800 |
*/ |
| 801 |
#define MIPS_SOFT 0x00 /* Software emulation ISA I */ |
| 802 |
#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ |
| 803 |
#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ |
| 804 |
#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ |
| 805 |
#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ |
| 806 |
#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ |
| 807 |
#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ |
| 808 |
#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ |
| 809 |
|
| 810 |
#ifdef ENABLE_MIPS_TX3900 |
| 811 |
#include <mips/r3900regs.h> |
| 812 |
#endif |
| 813 |
#ifdef MIPS3_5900 |
| 814 |
#include <mips/r5900regs.h> |
| 815 |
#endif |
| 816 |
#ifdef MIPS64_SB1 |
| 817 |
#include <mips/sb1regs.h> |
| 818 |
#endif |
| 819 |
|
| 820 |
#endif /* _MIPS_CPUREGS_H_ */ |
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