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#define MIPS_CPU_TYPES_H |
#define MIPS_CPU_TYPES_H |
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/* |
/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: mips_cpu_types.h,v 1.13 2006/01/11 19:20:08 debug Exp $ |
* $Id: mips_cpu_types.h,v 1.19 2007/02/10 13:31:20 debug Exp $ |
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* |
* |
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* MIPS CPU types. |
* MIPS CPU types. |
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*/ |
*/ |
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#include <misc.h> |
#include <misc.h> |
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/* MIPS CPU types: */ |
/* MIPS CPU types: */ |
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#include "cpuregs.h" |
#include "mips_cpuregs.h" |
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#define EXC3K 3 |
#define EXC3K 3 |
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#define EXC4K 4 |
#define EXC4K 4 |
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*/ |
*/ |
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#define MIPS_CPU_TYPE_DEFS { \ |
#define MIPS_CPU_TYPE_DEFS { \ |
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{ "R2000", MIPS_R2000, 0x00, NOLLSC, EXC3K, MMU3K, 1, 64, 1,13,2,1,13,2,1, 0, 0, 0 }, \ |
{ "R2000", MIPS_R2000, 0x00, NOLLSC, EXC3K, MMU3K, 1, 0, 64, 1,13,2,1,13,2,1, 0, 0, 0 }, \ |
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{ "R2000A", MIPS_R2000, 0x10, NOLLSC, EXC3K, MMU3K, 1, 64, 1,13,2,1,13,2,1, 0, 0, 0 }, \ |
{ "R2000A", MIPS_R2000, 0x10, NOLLSC, EXC3K, MMU3K, 1, 0, 64, 1,13,2,1,13,2,1, 0, 0, 0 }, \ |
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{ "R3000", MIPS_R3000, 0x20, NOLLSC, EXC3K, MMU3K, 1, 64, 1,12,2,1,12,2,1, 0, 0, 0 }, \ |
{ "R3000", MIPS_R3000, 0x20, NOLLSC, EXC3K, MMU3K, 1, 0, 64, 1,12,2,1,12,2,1, 0, 0, 0 }, \ |
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{ "R3000A", MIPS_R3000, 0x30, NOLLSC, EXC3K, MMU3K, 1, 64, 1,13,2,1,13,2,1, 0, 0, 0 }, \ |
{ "R3000A", MIPS_R3000, 0x30, NOLLSC, EXC3K, MMU3K, 1, 0, 64, 1,13,2,1,13,2,1, 0, 0, 0 }, \ |
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{ "R6000", MIPS_R6000, 0x00, 0, EXC3K, MMU3K, 2, 32, 1,16,2,2,16,2,2, 0, 0, 0 }, /* instrs/cycle? */ \ |
{ "R6000", MIPS_R6000, 0x00, 0, EXC3K, MMU3K, 2, 0, 32, 1,16,2,2,16,2,2, 0, 0, 0 }, /* instrs/cycle? */ \ |
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{ "R4000", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 48, 2,13,4,2,13,4,2,19, 6, 1 }, \ |
{ "R4000", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 0, 48, 2,13,4,2,13,4,2,19, 6, 1 }, \ |
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{ "R4000PC", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 48, 2,13,4,2,13,4,2, 0, 6, 1 }, \ |
{ "R4000PC", MIPS_R4000, 0x00, DCOUNT, EXC4K, MMU4K, 3, 0, 48, 2,13,4,2,13,4,2, 0, 6, 1 }, \ |
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{ "R10000", MIPS_R10000,0x26, 0, EXC4K, MMU10K, 4, 64, 4,15,6,2,15,5,2,20, 6, 1 }, \ |
{ "R10000", MIPS_R10000,0x26, 0, EXC4K, MMU10K, 4, 0, 64, 4,15,6,2,15,5,2,20, 6, 1 }, \ |
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{ "R4200", MIPS_R4200, 0x00, 0, EXC4K, MMU4K, 3, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
{ "R4200", MIPS_R4200, 0x00, 0, EXC4K, MMU4K, 3, 0, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "R4300", MIPS_R4300, 0x00, 0, EXC4K, MMU4K, 3, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
{ "R4300", MIPS_R4300, 0x00, 0, EXC4K, MMU4K, 3, 0, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "R4100", MIPS_R4100, 0x00, 0, EXC4K, MMU4K, 3, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
{ "R4100", MIPS_R4100, 0x00, 0, EXC4K, MMU4K, 3, 0, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "VR4102", MIPS_R4100, 0x40, NOFPU, EXC4K, MMU4K, 3, 32, 2,12,0,0,10,0,0, 0, 0, 0 }, /* TODO: Bogus? */ \ |
{ "VR4102", MIPS_R4100, 0x40, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,12,0,0,10,0,0, 0, 0, 0 }, /* TODO: Bogus? */ \ |
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{ "VR4181", MIPS_R4100, 0x50, NOFPU, EXC4K, MMU4K, 3, 32, 2,14,4,0,13,4,0, 0, 0, 0 }, \ |
{ "VR4181", MIPS_R4100, 0x50, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,14,4,0,13,4,0, 0, 0, 0 }, \ |
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{ "VR4121", MIPS_R4100, 0x60, NOFPU, EXC4K, MMU4K, 3, 32, 2,14,4,0,13,4,0, 0, 0, 0 }, \ |
{ "VR4121", MIPS_R4100, 0x60, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,14,4,0,13,4,0, 0, 0, 0 }, \ |
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{ "VR4122", MIPS_R4100, 0x70, NOFPU, EXC4K, MMU4K, 3, 32, 2,15,5,0,14,4,0, 0, 0, 0 }, \ |
{ "VR4122", MIPS_R4100, 0x70, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,15,5,0,14,4,0, 0, 0, 0 }, \ |
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{ "VR4131", MIPS_R4100, 0x80, NOFPU, EXC4K, MMU4K, 3, 32, 2,14,5,0,14,5,0, 0, 0, 0 }, \ |
{ "VR4131", MIPS_R4100, 0x80, NOFPU, EXC4K, MMU4K, 3, 0, 32, 2,14,5,0,14,5,0, 0, 0, 0 }, \ |
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{ "R4400", MIPS_R4000, 0x40, DCOUNT, EXC4K, MMU4K, 3, 48, 2,14,4,1,14,4,1,20, 6, 1 }, \ |
{ "R4400", MIPS_R4000, 0x40, DCOUNT, EXC4K, MMU4K, 3, 0, 48, 2,14,4,1,14,4,1,20, 6, 1 }, \ |
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{ "R4600", MIPS_R4600, 0x00, DCOUNT, EXC4K, MMU4K, 3, 48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ |
{ "R4600", MIPS_R4600, 0x00, DCOUNT, EXC4K, MMU4K, 3, 0, 48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ |
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{ "R4700", MIPS_R4700, 0x00, 0, EXC4K, MMU4K, 3, 48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
{ "R4700", MIPS_R4700, 0x00, 0, EXC4K, MMU4K, 3, 0, 48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "R4650", MIPS_R4650, 0x00, 0, EXC4K, MMU4K, 3, 48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
{ "R4650", MIPS_R4650, 0x00, 0, EXC4K, MMU4K, 3, 0, 48, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* No DCOUNT? */ \ |
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{ "R8000", MIPS_R8000, 0, 0, EXC4K, MMU8K, 4, 192, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* 192 tlb entries? or 384? instrs/cycle? */ \ |
{ "R8000", MIPS_R8000, 0, 0, EXC4K, MMU8K, 4, 0, 192, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* 192 tlb entries? or 384? instrs/cycle? */ \ |
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{ "R12000", MIPS_R12000,0x23, 0, EXC4K, MMU10K, 4, 64, 4,15,6,2,15,5,2,23, 6, 1 }, \ |
{ "R12000", MIPS_R12000,0x23, 0, EXC4K, MMU10K, 4, 0, 64, 4,15,6,2,15,5,2,23, 6, 1 }, \ |
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{ "R14000", MIPS_R14000,0, 0, EXC4K, MMU10K, 4, 64, 4,15,6,2,15,5,2,22, 6, 1 }, \ |
{ "R14000", MIPS_R14000,0, 0, EXC4K, MMU10K, 4, 0, 64, 4,15,6,2,15,5,2,22, 6, 1 }, \ |
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{ "R5000", MIPS_R5000, 0x21, DCOUNT, EXC4K, MMU4K, 4, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* 2way I,D; instrs/cycle? */ \ |
{ "R5000", MIPS_R5000, 0x21, DCOUNT, EXC4K, MMU4K, 4, 0, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* 2way I,D; instrs/cycle? */ \ |
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{ "R5900", MIPS_R5900, 0x20, 0, EXC4K, MMU4K, 3, 48, 4,14,6,2,13,6,2, 0, 0, 0 }, /* instrs/cycle? */ \ |
{ "R5900", MIPS_R5900, 0x20, 0, EXC4K, MMU4K, 3, 0, 48, 4,14,6,2,13,6,2, 0, 0, 0 }, /* instrs/cycle? */ \ |
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{ "TX3920", MIPS_TX3900,0x30, 0, EXC32, MMU32, 1, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \ |
{ "TX3920", MIPS_TX3900,0x30, 0, EXC32, MMU32, 1, 0, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \ |
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{ "TX7901", 0x38, 0x01, 0, EXC4K, MMU4K, 64, 48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \ |
{ "TX7901", MIPS_TX7900,0x01, 0, EXC4K, MMU4K, 3, 1, 48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: bogus? */ \ |
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{ "VR5432", MIPS_R5400, 13, 0, EXC4K, MMU4K, 4, 48, 4,15,0,0,15,0,0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? linesize? etc */ \ |
{ "VR5432", MIPS_R5400, 13, 0, EXC4K, MMU4K, 4, 0, 48, 4,15,0,0,15,0,0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? linesize? etc */ \ |
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{ "RM5200", MIPS_RM5200,0xa0, 0, EXC4K, MMU4K, 4, 48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? */ \ |
{ "RM5200", MIPS_RM5200,0xa0, 0, EXC4K, MMU4K, 4, 0, 48, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* DCOUNT? instrs/cycle? */ \ |
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{ "RM7000", MIPS_RM7000,0x0 /* ? */,DCOUNT, EXC4K, MMU4K, 4, 48, 4,14,5,1,14,5,1,18, 6, 1 }, /* instrs/cycle? cachelinesize & assoc.? RM7000A? */ \ |
{ "RM7000", MIPS_RM7000,0x0 /* ? */,DCOUNT, EXC4K, MMU4K, 4, 0, 48, 4,14,5,1,14,5,1,18, 6, 1 }, /* instrs/cycle? cachelinesize & assoc.? RM7000A? */ \ |
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{ "RM7900", 0x34 /*?*/, 0x0 /* ? */,DCOUNT,EXC4K, MMU4K, 4, 64, 4,14,5,1,14,5,1,18, 6, 1 }, /* instrs/cycle? cachelinesize? assoc = 4ways for all */ \ |
{ "RM7900", 0x34 /*?*/, 0x0 /* ? */,DCOUNT,EXC4K, MMU4K, 4, 0, 64, 4,14,5,1,14,5,1,18, 6, 1 }, /* instrs/cycle? cachelinesize? assoc = 4ways for all */ \ |
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{ "RM9000", 0x34 /*?*/, 0x0 /* ? */,DCOUNT,EXC4K, MMU4K, 4, 48, 4,14,5,1,14,5,1,18, 6, 1 }, /* This is totally bogus */ \ |
{ "RM9000", 0x34 /*?*/, 0x0 /* ? */,DCOUNT,EXC4K, MMU4K, 4, 0, 48, 4,14,5,1,14,5,1,18, 6, 1 }, /* This is totally bogus */ \ |
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{ "RC32334", MIPS_RC32300,0x00, 0, EXC32, MMU4K, 32, 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ |
{ "RC32334", MIPS_RC32300,0x00, 0, EXC32, MMU4K, 32, 1, 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ |
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{ "4Kc", 0x100+MIPS_4Kc, 1, 0, EXC32, MMU32, 32, 16, 4,14,4,2,14,4,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
{ "4Kc", 0x100+MIPS_4Kc, 1, 0, EXC32, MMU32, 32, 1, 16, 4,14,4,2,14,4,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
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{ "5Kc", 0x100+MIPS_5Kc, 1, 0, EXC64, MMU64, 64, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
{ "4KEc", 0x100+MIPS_4KEc_R2, 1, 0, EXC32, MMU32, 32, 2, 16, 4,14,4,2,14,4,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
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{ "BCM4710", 0x000240, 0x00, 0, EXC32, MMU32, 32, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
{ "5Kc", 0x100+MIPS_5Kc, 1, 0, EXC64, MMU64, 64, 1, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
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{ "BCM4712", 0x000290, 0x07, 0, EXC32, MMU32, 32, 32, 2,13,4,1,12,4,1, 0, 0, 0 }, /* 2ways I, 2ways D */ \ |
{ "5KE", 0x100+MIPS_5KE, 1, 0, EXC64, MMU64, 64, 2, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
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{ "AU1000", 0x000301, 0x00, 0, EXC32, MMU32, 32, 32, 2,14,5,2,14,5,2, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
{ "BCM4710", 0x000240, 0x00, 0, EXC32, MMU32, 32, 1, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "AU1500", 0x010301, 0x00, 0, EXC32, MMU32, 32, 32, 2,14,5,2,14,5,2, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
{ "BCM4712", 0x000290, 0x07, 0, EXC32, MMU32, 32, 1, 32, 2,13,4,1,12,4,1, 0, 0, 0 }, /* 2ways I, 2ways D */ \ |
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{ "AU1100", 0x020301, 0x00, 0, EXC32, MMU32, 32, 32, 2,14,5,2,14,5,2, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
{ "AU1000", 0x00302, 0x01, 0, EXC32, MMU32, 32, 1, 32, 2,14,5,2,14,5,2, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "SB1", 0x000401, 0x00, 0, EXC64, MMU64, 64, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
{ "AU1500", 0x10302, 0x02, 0, EXC32, MMU32, 32, 1, 32, 2,14,5,4,14,5,4, 0, 0, 0 }, \ |
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{ "SR7100", 0x000504, 0x00, 0, EXC64, MMU64, 64, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
{ "AU1100", 0x20302, 0x01, 0, EXC32, MMU32, 32, 1, 32, 2,14,5,2,14,5,2, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "Allegrex", 0x000000, 0x00, 0, EXC32, MMU32, 2, 4, 1,14,6,2,14,6,2, 0, 0, 0 }, \ |
{ "SB1", 0x000401, 0x00, 0, EXC64, MMU64, 64, 1, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "SR7100", 0x000504, 0x00, 0, EXC64, MMU64, 64, 1, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "Allegrex", 0x000000, 0x00, 0, EXC32, MMU32, 2, 0, 4, 1,14,6,2,14,6,2, 0, 0, 0 }, \ |
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{ NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } |
{ NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } |
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#endif /* MIPS_CPU_TYPES_H */ |
#endif /* MIPS_CPU_TYPES_H */ |