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/* gxemul: $Id: mc146818reg.h,v 1.4 2005/03/05 12:34:02 debug Exp $ */ |
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#ifndef MC146818_REG_H |
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#define MC146818_REG_H |
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#ifndef __P |
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#define __P(x) x |
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#endif |
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/* $NetBSD: mc146818reg.h,v 1.2 1997/03/12 06:53:42 cgd Exp $ */ |
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/* |
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* Copyright (c) 1995 Carnegie-Mellon University. |
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* All rights reserved. |
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* |
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* Permission to use, copy, modify and distribute this software and |
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* its documentation is hereby granted, provided that both the copyright |
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* notice and this permission notice appear in all copies of the |
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* software, derivative works or modified versions, and any portions |
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* thereof, and that both notices appear in supporting documentation. |
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* |
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" |
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND |
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. |
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* |
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* Carnegie Mellon requests users of this software to return to |
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* |
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU |
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* School of Computer Science |
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* Carnegie Mellon University |
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* Pittsburgh PA 15213-3890 |
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* |
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* any improvements or extensions that they make and grant Carnegie the |
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* rights to redistribute these changes. |
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*/ |
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|
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/* |
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* Definitions for the Motorola MC146818A Real Time Clock. |
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* They also apply for the (compatible) Dallas Semicontuctor DS1287A RTC. |
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* |
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* Though there are undoubtedly other (better) sources, this material was |
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* culled from the DEC "KN121 System Module Programmer's Reference |
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* Information." |
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* |
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* The MC146818A has 16 registers. The first 10 contain time-of-year |
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* and alarm data. The rest contain various control and status bits. |
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* |
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* To read or write the registers, one writes the register number to |
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* the RTC's control port, then either reads from or writes the new |
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* data to the RTC's data port. Since the locations of these ports |
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* and the method used to access them can be machine-dependent, the |
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* low-level details of reading and writing the RTC's registers are |
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* handled by machine-specific functions. |
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* |
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* The time-of-year and alarm data can be expressed in either binary |
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* or BCD, and they are selected by a bit in register B. |
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* |
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* The "hour" time-of-year and alarm fields can either be expressed in |
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* AM/PM format, or in 24-hour format. If AM/PM format is chosen, the |
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* hour fields can have the values: 1-12 and 81-92 (the latter being |
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* PM). If the 24-hour format is chosen, they can have the values |
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* 0-24. The hour format is selectable by a bit in register B. |
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* (XXX IS AM/PM MODE DESCRIPTION CORRECT?) |
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* |
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* It is assumed the if systems are going to use BCD (rather than |
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* binary) mode, or AM/PM hour format, they'll do the appropriate |
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* conversions in machine-dependent code. Also, if the clock is |
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* switched between BCD and binary mode, or between AM/PM mode and |
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* 24-hour mode, the time-of-day and alarm registers are NOT |
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* automatically reset; they must be reprogrammed with correct values. |
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*/ |
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|
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/* |
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* The registers, and the bits within each register. |
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*/ |
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|
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#define MC_SEC 0x0 /* Time of year: seconds (0-59) */ |
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#define MC_ASEC 0x1 /* Alarm: seconds */ |
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#define MC_MIN 0x2 /* Time of year: minutes (0-59) */ |
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#define MC_AMIN 0x3 /* Alarm: minutes */ |
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#define MC_HOUR 0x4 /* Time of year: hour (see above) */ |
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#define MC_AHOUR 0x5 /* Alarm: hour */ |
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#define MC_DOW 0x6 /* Time of year: day of week (1-7) */ |
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#define MC_DOM 0x7 /* Time of year: day of month (1-31) */ |
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#define MC_MONTH 0x8 /* Time of year: month (1-12) */ |
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#define MC_YEAR 0x9 /* Time of year: year in century (0-99) */ |
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|
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#define MC_REGA 0xa /* Control register A */ |
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|
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#define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ |
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#define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ |
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#define MC_REGA_UIP 0x80 /* Update in progress; read only. */ |
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|
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#define MC_REGB 0xb /* Control register B */ |
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|
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#define MC_REGB_DSE 0x01 /* Daylight Savings Enable */ |
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#define MC_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */ |
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#define MC_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */ |
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#define MC_REGB_SQWE 0x08 /* Square Wave Enable */ |
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#define MC_REGB_UIE 0x10 /* Update End interrupt enable */ |
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#define MC_REGB_AIE 0x20 /* Alarm interrupt enable */ |
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#define MC_REGB_PIE 0x40 /* Periodic interrupt enable */ |
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#define MC_REGB_SET 0x80 /* Allow time to be set; stops updates */ |
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|
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#define MC_REGC 0xc /* Control register C */ |
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|
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/* MC_REGC_UNUSED 0x0f UNUSED */ |
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#define MC_REGC_UF 0x10 /* Update End interrupt flag */ |
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#define MC_REGC_AF 0x20 /* Alarm interrupt flag */ |
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#define MC_REGC_PF 0x40 /* Periodic interrupt flag */ |
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#define MC_REGC_IRQF 0x80 /* Interrupt request pending flag */ |
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|
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#define MC_REGD 0xd /* Control register D */ |
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|
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/* MC_REGD_UNUSED 0x7f UNUSED */ |
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#define MC_REGD_VRT 0x80 /* Valid RAM and Time bit */ |
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|
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|
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#define MC_NREGS 0xe /* 14 registers; CMOS follows */ |
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#define MC_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */ |
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|
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#define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */ |
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#define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */ |
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|
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/* |
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* Periodic Interrupt Rate Select constants (Control register A) |
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*/ |
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#define MC_RATE_NONE 0x0 /* No periodic interrupt */ |
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#define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */ |
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#define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */ |
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#define MC_RATE_8192_Hz 0x3 /* 122.070 us period */ |
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#define MC_RATE_4096_Hz 0x4 /* 244.141 us period */ |
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#define MC_RATE_2048_Hz 0x5 /* 488.281 us period */ |
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#define MC_RATE_1024_Hz 0x6 /* 976.562 us period */ |
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#define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */ |
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#define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */ |
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#define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */ |
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#define MC_RATE_64_Hz 0xa /* 15.625 ms period */ |
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#define MC_RATE_32_Hz 0xb /* 31.25 ms period */ |
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#define MC_RATE_16_Hz 0xc /* 62.5 ms period */ |
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#define MC_RATE_8_Hz 0xd /* 125 ms period */ |
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#define MC_RATE_4_Hz 0xe /* 250 ms period */ |
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#define MC_RATE_2_Hz 0xf /* 500 ms period */ |
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|
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/* |
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* Time base (divisor select) constants (Control register A) |
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*/ |
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#define MC_BASE_4_MHz 0x00 /* 4MHz crystal */ |
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#define MC_BASE_1_MHz 0x10 /* 1MHz crystal */ |
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#define MC_BASE_32_KHz 0x20 /* 32KHz crystal */ |
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#define MC_BASE_NONE 0x60 /* actually, both of these reset */ |
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#define MC_BASE_RESET 0x70 |
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|
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/* |
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* RTC register/NVRAM read and write functions -- machine-dependent. |
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* Appropriately manipulate RTC registers to get/put data values. |
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*/ |
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u_int mc146818_read __P((void *sc, u_int reg)); |
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void mc146818_write __P((void *sc, u_int reg, u_int datum)); |
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/* |
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* A collection of TOD/Alarm registers. |
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*/ |
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typedef u_int mc_todregs[MC_NTODREGS]; |
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/* |
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* Get all of the TOD/Alarm registers |
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* Must be called at splhigh(), and with the RTC properly set up. |
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*/ |
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#define MC146818_GETTOD(sc, regs) \ |
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do { \ |
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int i; \ |
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\ |
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/* update in progress; spin loop */ \ |
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while (mc146818_read(sc, MC_REGA) & MC_REGA_UIP) \ |
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; \ |
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\ |
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/* read all of the tod/alarm regs */ \ |
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for (i = 0; i < MC_NTODREGS; i++) \ |
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(*regs)[i] = mc146818_read(sc, i); \ |
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} while (0); |
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|
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/* |
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* Set all of the TOD/Alarm registers |
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* Must be called at splhigh(), and with the RTC properly set up. |
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*/ |
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#define MC146818_PUTTOD(sc, regs) \ |
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do { \ |
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int i; \ |
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\ |
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/* stop updates while setting */ \ |
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mc146818_write(sc, MC_REGB, \ |
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mc146818_read(sc, MC_REGB) | MC_REGB_SET); \ |
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\ |
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/* write all of the tod/alarm regs */ \ |
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for (i = 0; i < MC_NTODREGS; i++) \ |
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mc146818_write(sc, i, (*regs)[i]); \ |
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\ |
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/* reenable updates */ \ |
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mc146818_write(sc, MC_REGB, \ |
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mc146818_read(sc, MC_REGB) & ~MC_REGB_SET); \ |
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} while (0); |
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#endif |
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