src/include/jazz_r4030_dma.h

/*  gxemul: $Id: jazz_r4030_dma.h,v 1.4 2005/06/02 12:31:40 debug Exp $  */
/*      $NetBSD: dma.h,v 1.2 2001/07/24 16:26:53 tsutsui Exp $  */
/*      $OpenBSD: dma.h,v 1.3 1997/04/19 17:19:51 pefo Exp $    */

#ifndef __JAZZ_R4030_DMA
#define __JAZZ_R4030_DMA

#ifndef GXEMUL
#define GXEMUL
#endif

/*
 * Copyright (c) 1996 Per Fogelstrom
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *      This product includes software developed by Per Fogelstrom.
 * 4. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 *  Hardware dma registers.
 */
typedef volatile struct {
        int32_t         dma_mode;
        int32_t         pad1;
        int32_t         dma_enab;
        int32_t         pad2;
        int32_t         dma_count;
        int32_t         pad3;
        int32_t         dma_addr;
        int32_t         pad4;
} DmaReg, *pDmaReg;

#define R4030_DMA_MODE_40NS     0x00    /* Device dma timing */
#define R4030_DMA_MODE_80NS     0x01    /* Device dma timing */
#define R4030_DMA_MODE_120NS    0x02    /* Device dma timing */
#define R4030_DMA_MODE_160NS    0x03    /* Device dma timing */
#define R4030_DMA_MODE_200NS    0x04    /* Device dma timing */
#define R4030_DMA_MODE_240NS    0x05    /* Device dma timing */
#define R4030_DMA_MODE_280NS    0x06    /* Device dma timing */
#define R4030_DMA_MODE_320NS    0x07    /* Device dma timing */
#define R4030_DMA_MODE_8                0x08    /* Device 8 bit  */
#define R4030_DMA_MODE_16       0x10    /* Device 16 bit */
#define R4030_DMA_MODE_32       0x18    /* Device 32 bit */
#define R4030_DMA_MODE_INT      0x20    /* Interrupt when done */
#define R4030_DMA_MODE_BURST    0x40    /* Burst mode (Rev 2 only) */
#define R4030_DMA_MODE_FAST     0x80    /* Fast dma cycle (Rev 2 only) */
#define R4030_DMA_MODE          0xff    /* Mode register bits */
#define DMA_DIR_WRITE           0x100   /* Software direction status */
#define DMA_DIR_READ            0x000   /* Software direction status */

#define R4030_DMA_ENAB_RUN      0x01    /* Enable dma */
#define R4030_DMA_ENAB_READ     0x00    /* Read from device */
#define R4030_DMA_ENAB_WRITE    0x02    /* Write to device */
#define R4030_DMA_ENAB_TC_IE    0x100   /* Terminal count int enable */
#define R4030_DMA_ENAB_ME_IE    0x200   /* Memory error int enable */
#define R4030_DMA_ENAB_TL_IE    0x400   /* Translation limit int enable */

#define R4030_DMA_COUNT_MASK    0x000fffff /* Byte count mask */

/*
 *  Structure used to control dma.
 */

#ifndef GXEMUL
typedef struct dma_softc {
        struct device   sc_dev;         /* use as a device */
        struct esp_softc *sc_esp;
        bus_addr_t      dma_va;         /* Viritual address for transfer */
        int             mode;           /* Mode register value and direction */
        jazz_dma_pte_t  *pte_base;      /* Pointer to dma tlb array */
        int             pte_size;       /* Size of pte allocated pte array */
        pDmaReg         dma_reg;        /* Pointer to dma registers */
        int             sc_active;      /* Active flag */
        void (*reset)(struct dma_softc *);      /* Reset routine pointer */
        void (*enintr)(struct dma_softc *);     /* Int enab routine pointer */
        void (*map)(struct dma_softc *, char *, size_t, int);
                                                /* Map a dma viritual area */
        void (*start)(struct dma_softc *, caddr_t, size_t, int);
                                                /* Start routine pointer */
        int (*isintr)(struct dma_softc *);      /* Int check routine pointer */
        int (*intr)(struct dma_softc *);        /* Interrupt routine pointer */
        void (*end)(struct dma_softc *);        /* Interrupt routine pointer */
} dma_softc_t;
#endif  /*  not in gxemul  */

#define DMA_TO_DEV      0
#define DMA_FROM_DEV    1

#define DMA_RESET(r)            ((r->reset)(r))
#define DMA_START(a, b, c, d)   ((a->start)(a, b, c, d))
#define DMA_MAP(a, b, c, d)     ((a->map)(a, b, c, d))
#define DMA_INTR(r)             ((r->intr)(r))
#define DMA_DRAIN(r)
#define DMA_END(r)              ((r->end)(r))

#ifndef GXEMUL
void picaDmaInit __P((void));
void picaDmaTLBAlloc __P((dma_softc_t *));
void picaDmaTLBFree __P((dma_softc_t *));
void picaDmaMap __P((struct dma_softc *, char *, size_t, int));
void picaDmaStart __P((struct dma_softc *, char *, size_t, int));
void picaDmaFlush __P((struct dma_softc *, char *, size_t, int));
void asc_dma_init __P((struct dma_softc *));
void fdc_dma_init __P((struct dma_softc *));
#endif  /*  not in gxemul  */

#endif  /*  __JAZZ_R4030_DMA  */
1	/* gxemul: $Id: jazz_r4030_dma.h,v 1.4 2005/06/02 12:31:40 debug Exp $ */
2	/* $NetBSD: dma.h,v 1.2 2001/07/24 16:26:53 tsutsui Exp $ */
3	/* $OpenBSD: dma.h,v 1.3 1997/04/19 17:19:51 pefo Exp $ */
4
5	#ifndef __JAZZ_R4030_DMA
6	#define __JAZZ_R4030_DMA
7
8	#ifndef GXEMUL
9	#define GXEMUL
10	#endif
11
12	/*
13	* Copyright (c) 1996 Per Fogelstrom
14	* All rights reserved.
15	*
16	* Redistribution and use in source and binary forms, with or without
17	* modification, are permitted provided that the following conditions
18	* are met:
19	* 1. Redistributions of source code must retain the above copyright
20	* notice, this list of conditions and the following disclaimer.
21	* 2. Redistributions in binary form must reproduce the above copyright
22	* notice, this list of conditions and the following disclaimer in the
23	* documentation and/or other materials provided with the distribution.
24	* 3. All advertising materials mentioning features or use of this software
25	* must display the following acknowledgement:
26	* This product includes software developed by Per Fogelstrom.
27	* 4. The name of the author may not be used to endorse or promote products
28	* derived from this software without specific prior written permission
29	*
30	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
31	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
32	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
33	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
34	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
35	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
39	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40	*/
41
42	/*
43	* Hardware dma registers.
44	*/
45	typedef volatile struct {
46	int32_t dma_mode;
47	int32_t pad1;
48	int32_t dma_enab;
49	int32_t pad2;
50	int32_t dma_count;
51	int32_t pad3;
52	int32_t dma_addr;
53	int32_t pad4;
54	} DmaReg, *pDmaReg;
55
56	#define R4030_DMA_MODE_40NS 0x00 /* Device dma timing */
57	#define R4030_DMA_MODE_80NS 0x01 /* Device dma timing */
58	#define R4030_DMA_MODE_120NS 0x02 /* Device dma timing */
59	#define R4030_DMA_MODE_160NS 0x03 /* Device dma timing */
60	#define R4030_DMA_MODE_200NS 0x04 /* Device dma timing */
61	#define R4030_DMA_MODE_240NS 0x05 /* Device dma timing */
62	#define R4030_DMA_MODE_280NS 0x06 /* Device dma timing */
63	#define R4030_DMA_MODE_320NS 0x07 /* Device dma timing */
64	#define R4030_DMA_MODE_8 0x08 /* Device 8 bit */
65	#define R4030_DMA_MODE_16 0x10 /* Device 16 bit */
66	#define R4030_DMA_MODE_32 0x18 /* Device 32 bit */
67	#define R4030_DMA_MODE_INT 0x20 /* Interrupt when done */
68	#define R4030_DMA_MODE_BURST 0x40 /* Burst mode (Rev 2 only) */
69	#define R4030_DMA_MODE_FAST 0x80 /* Fast dma cycle (Rev 2 only) */
70	#define R4030_DMA_MODE 0xff /* Mode register bits */
71	#define DMA_DIR_WRITE 0x100 /* Software direction status */
72	#define DMA_DIR_READ 0x000 /* Software direction status */
73
74	#define R4030_DMA_ENAB_RUN 0x01 /* Enable dma */
75	#define R4030_DMA_ENAB_READ 0x00 /* Read from device */
76	#define R4030_DMA_ENAB_WRITE 0x02 /* Write to device */
77	#define R4030_DMA_ENAB_TC_IE 0x100 /* Terminal count int enable */
78	#define R4030_DMA_ENAB_ME_IE 0x200 /* Memory error int enable */
79	#define R4030_DMA_ENAB_TL_IE 0x400 /* Translation limit int enable */
80
81	#define R4030_DMA_COUNT_MASK 0x000fffff /* Byte count mask */
82
83	/*
84	* Structure used to control dma.
85	*/
86
87	#ifndef GXEMUL
88	typedef struct dma_softc {
89	struct device sc_dev; /* use as a device */
90	struct esp_softc *sc_esp;
91	bus_addr_t dma_va; /* Viritual address for transfer */
92	int mode; /* Mode register value and direction */
93	jazz_dma_pte_t pte_base; / Pointer to dma tlb array */
94	int pte_size; /* Size of pte allocated pte array */
95	pDmaReg dma_reg; /* Pointer to dma registers */
96	int sc_active; /* Active flag */
97	void (reset)(struct dma_softc ); /* Reset routine pointer */
98	void (enintr)(struct dma_softc ); /* Int enab routine pointer */
99	void (map)(struct dma_softc , char *, size_t, int);
100	/* Map a dma viritual area */
101	void (start)(struct dma_softc , caddr_t, size_t, int);
102	/* Start routine pointer */
103	int (isintr)(struct dma_softc ); /* Int check routine pointer */
104	int (intr)(struct dma_softc ); /* Interrupt routine pointer */
105	void (end)(struct dma_softc ); /* Interrupt routine pointer */
106	} dma_softc_t;
107	#endif /* not in gxemul */
108
109	#define DMA_TO_DEV 0
110	#define DMA_FROM_DEV 1
111
112	#define DMA_RESET(r) ((r->reset)(r))
113	#define DMA_START(a, b, c, d) ((a->start)(a, b, c, d))
114	#define DMA_MAP(a, b, c, d) ((a->map)(a, b, c, d))
115	#define DMA_INTR(r) ((r->intr)(r))
116	#define DMA_DRAIN(r)
117	#define DMA_END(r) ((r->end)(r))
118
119	#ifndef GXEMUL
120	void picaDmaInit __P((void));
121	void picaDmaTLBAlloc __P((dma_softc_t *));
122	void picaDmaTLBFree __P((dma_softc_t *));
123	void picaDmaMap __P((struct dma_softc , char , size_t, int));
124	void picaDmaStart __P((struct dma_softc , char , size_t, int));
125	void picaDmaFlush __P((struct dma_softc , char , size_t, int));
126	void asc_dma_init __P((struct dma_softc *));
127	void fdc_dma_init __P((struct dma_softc *));
128	#endif /* not in gxemul */
129
130	#endif /* __JAZZ_R4030_DMA */