| 1 |
/* gxemul: $Id: imcreg.h,v 1.2 2005/03/05 12:34:02 debug Exp $ */ |
| 2 |
/* $NetBSD: imcreg.h,v 1.2 2002/03/13 13:12:26 simonb Exp $ */ |
| 3 |
|
| 4 |
/* |
| 5 |
* Copyright (c) 2001 Rafal K. Boni |
| 6 |
* All rights reserved. |
| 7 |
* |
| 8 |
* Redistribution and use in source and binary forms, with or without |
| 9 |
* modification, are permitted provided that the following conditions |
| 10 |
* are met: |
| 11 |
* 1. Redistributions of source code must retain the above copyright |
| 12 |
* notice, this list of conditions and the following disclaimer. |
| 13 |
* 2. Redistributions in binary form must reproduce the above copyright |
| 14 |
* notice, this list of conditions and the following disclaimer in the |
| 15 |
* documentation and/or other materials provided with the distribution. |
| 16 |
* 3. The name of the author may not be used to endorse or promote products |
| 17 |
* derived from this software without specific prior written permission. |
| 18 |
* |
| 19 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 20 |
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 21 |
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 22 |
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 23 |
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 24 |
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 25 |
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 26 |
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 27 |
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 28 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 29 |
*/ |
| 30 |
|
| 31 |
#ifndef _ARCH_SGIMIPS_DEV_IMCREG_H_ |
| 32 |
#define _ARCH_SGIMIPS_DEV_IMCREG_H_ |
| 33 |
|
| 34 |
#define IMC_CPUCTRL0 0x1fa00004 /* CPU control, register 0 */ |
| 35 |
|
| 36 |
#define IMC_CPUCTRL0_REFMASK 0x0000000f /* # lines to refresh */ |
| 37 |
#define IMC_CPUCTRL0_RFE 0x00000010 /* refresh enable */ |
| 38 |
#define IMC_CPUCTRL0_GPR 0x00000020 /* GIO parity enable */ |
| 39 |
#define IMC_CPUCTRL0_MPR 0x00000040 /* memory parity enable */ |
| 40 |
#define IMC_CPUCTRL0_CPR 0x00000080 /* cpu bus parity enable */ |
| 41 |
#define IMC_CPUCTRL0_WDOG 0x00000100 /* watchdog enable */ |
| 42 |
#define IMC_CPUCTRL0_SIN 0x00000200 /* reset system */ |
| 43 |
#define IMC_CPUCTRL0_GRR 0x00000400 /* graphics reset */ |
| 44 |
#define IMC_CPUCTRL0_ENLOCK 0x00000800 /* enable EISA memory lock */ |
| 45 |
#define IMC_CPUCTRL0_CMDPAR 0x00001000 /* SysCmd parity enable */ |
| 46 |
#define IMC_CPUCTRL0_INTENA 0x00002000 /* enable CPU interrupts */ |
| 47 |
#define IMC_CPUCTRL0_SNOOPENA 0x00004000 /* enable gfx DMA snoop */ |
| 48 |
#define IMC_CPUCTRL0_PROM_WRENA 0x00008000 /* disable buserr on PROM |
| 49 |
* writes */ |
| 50 |
#define IMC_CPUCTRL0_WRST 0x00010000 /* warm restart (reset cpu) */ |
| 51 |
/* Bit 17 reserved 0x00020000 */ |
| 52 |
#define IMC_CPUCTRL0_LITTLE 0x00040000 /* MC little-endian toggle */ |
| 53 |
#define IMC_CPUCTRL0_WRRST 0x00080000 /* cpu warm reset */ |
| 54 |
#define IMC_CPUCTRL0_MUXHWMSK 0x01f00000 /* MUX fifo high-water mask */ |
| 55 |
#define IMC_CPUCTRL0_BADPAR 0x02000000 /* generate bad parity on |
| 56 |
* CPU->memory writes */ |
| 57 |
#define IMC_CPUCTRL0_NCHKMEMPAR 0x04000000 /* disable CPU parity check |
| 58 |
* on memory reads. */ |
| 59 |
#define IMC_CPUCTRL0_BACK2 0x08000000 /* enable back2back GIO wrt */ |
| 60 |
#define IMC_CPUCTRL0_BUSRTMSK 0xf0000000 /* stall cycle for berr data */ |
| 61 |
|
| 62 |
#define IMC_CPUCTRL1 0x1fa0000c /* CPU control, register 1 */ |
| 63 |
#define IMC_CPUCTRL1_MCHWMSK 0x0000000f /* MC FIFO high water mask */ |
| 64 |
#define IMC_CPUCTRL1_ABORTEN 0x00000010 /* Enable GIO bus timeouts */ |
| 65 |
/* Bits 5 - 11 reserved 0x00000fe0 */ |
| 66 |
#define IMC_CPUCTRL1_HPCFX 0x00001000 /* HPC endian fix */ |
| 67 |
#define IMC_CPUCTRL1_HPCLITTLE 0x00002000 /* HPC DMA is little-endian */ |
| 68 |
#define IMC_CPUCTRL1_EXP0FX 0x00004000 /* EXP0 endian fix */ |
| 69 |
#define IMC_CPUCTRL1_EXP0LITTLE 0x00008000 /* EXP0 DMA is little-endian */ |
| 70 |
#define IMC_CPUCTRL1_EXP1FX 0x00010000 /* EXP1 endian fix */ |
| 71 |
#define IMC_CPUCTRL1_EXP1LITTLE 0x00020000 /* EXP1 DMA is little-endian */ |
| 72 |
|
| 73 |
#define IMC_WDOG 0x1fa00014 /* Watchdog counter */ |
| 74 |
#define IMC_WDOG_MASK 0x001fffff /* counter mask */ |
| 75 |
|
| 76 |
#define IMC_SYSID 0x1fa0001c /* MC revision register */ |
| 77 |
#define IMC_SYSID_REVMASK 0x0000000f /* MC revision mask */ |
| 78 |
#define IMC_SYSID_HAVEISA 0x00000010 /* EISA present */ |
| 79 |
|
| 80 |
#define IMC_RPSSDIV 0x1fa0002c /* RPSS divider */ |
| 81 |
#define IMC_RPSSDIV_DIVMSK 0x000000ff /* RPC divider mask */ |
| 82 |
#define IMC_RPSSDIV_INCMSK 0x0000ff00 /* RPC increment mask */ |
| 83 |
|
| 84 |
#define IMC_EEPROM 0x1fa00034 /* EEPROM serial interface */ |
| 85 |
/* Bit 1 is reserved 0x00000001 */ |
| 86 |
#define IMC_EEPROM_CS 0x00000002 /* EEPROM chip select */ |
| 87 |
#define IMC_EEPROM_SCK 0x00000004 /* EEPROM serial clock */ |
| 88 |
#define IMC_EEPROM_SO 0x00000008 /* Serial data to EEPROM */ |
| 89 |
#define IMC_EEPROM_SI 0x00000010 /* Serial data from EEPROM */ |
| 90 |
|
| 91 |
#define IMC_CTRLD 0x1fa00044 /* Refresh counter preload */ |
| 92 |
#define IMC_CTRLD_MSK 0x000000ff /* Counter preload mask */ |
| 93 |
|
| 94 |
#define IMC_REFCTR 0x1fa0004c /* Refresh counter */ |
| 95 |
#define IMC_REFCTR_MSK 0x000000ff /* Refresh counter mask */ |
| 96 |
|
| 97 |
#define IMC_GIO64ARB 0x1fa00084 /* GIO64 arbitration params */ |
| 98 |
#define IMC_GIO64ARB_HPC64 0x00000001 /* HPC addr size (32/64bit) */ |
| 99 |
#define IMC_GIO64ARB_GRX64 0x00000002 /* Gfx addr size (32/64bit) */ |
| 100 |
#define IMC_GIO64ARB_EXP064 0x00000004 /* EXP0 addr size (32/64bit) */ |
| 101 |
#define IMC_GIO64ARB_EXP164 0x00000008 /* EXP0 addr size (32/64bit) */ |
| 102 |
#define IMC_GIO64ARB_EISA64 0x00000010 /* EISA addr size (32/64bit) */ |
| 103 |
#define IMC_GIO64ARB_HPCEXP64 0x00000020 /* HPC2 addr size (32/64bit) */ |
| 104 |
#define IMC_GIO64ARB_GRXRT 0x00000040 /* Gfx is realtime device */ |
| 105 |
#define IMC_GIO64ARB_EXP0RT 0x00000080 /* EXP0 is realtime device */ |
| 106 |
#define IMC_GIO64ARB_EXP1RT 0x00000100 /* EXP1 is realtime device */ |
| 107 |
#define IMC_GIO64ARB_EISAMST 0x00000200 /* EISA can be busmaster */ |
| 108 |
#define IMC_GIO64ARB_ONEGIO 0x00000400 /* One one GIO64 bus */ |
| 109 |
#define IMC_GIO64ARB_GRXMST 0x00000800 /* Gfx can be busmaster */ |
| 110 |
#define IMC_GIO64ARB_EXP0MST 0x00001000 /* EXP0 can be busmaster */ |
| 111 |
#define IMC_GIO64ARB_EXP1MST 0x00002000 /* EXP1 can be busmaster */ |
| 112 |
#define IMC_GIO64ARB_EXP0PIPE 0x00004000 /* EXP0 is pipelined */ |
| 113 |
#define IMC_GIO64ARB_EXP1PIPE 0x00008000 /* EXP1 is pipelined */ |
| 114 |
|
| 115 |
#define IMC_CPUTIME 0x1fa0008c /* Arbiter CPU time period */ |
| 116 |
|
| 117 |
#define IMC_LBTIME 0x1fa0009c /* Arbiter long-burst time */ |
| 118 |
|
| 119 |
#define IMC_MEMCFG0 0x1fa000c4 /* Mem config, regsiter 0 */ |
| 120 |
|
| 121 |
#define IMC_MEMCFG1 0x1fa000cc /* Mem config, regsiter 1 */ |
| 122 |
|
| 123 |
#define IMC_CPU_MEMACC 0x1fa000d4 /* CPU mem access config */ |
| 124 |
|
| 125 |
#define IMC_GIO_MEMACC 0x1fa000dc /* GIO mem access config */ |
| 126 |
|
| 127 |
#define IMC_CPU_ERRADDR 0x1fa000e4 /* CPU error address */ |
| 128 |
|
| 129 |
#define IMC_CPU_ERRSTAT 0x1fa000ec /* CPU error status */ |
| 130 |
|
| 131 |
#define IMC_GIO_ERRADDR 0x1fa000f4 /* GIO error address */ |
| 132 |
|
| 133 |
#define IMC_GIO_ERRSTAT 0x1fa000fc /* GIO error status */ |
| 134 |
|
| 135 |
#endif /* _ARCH_SGIMIPS_DEV_IMCREG_H_ */ |
| 136 |
|
Parent Directory
| 
Revision Log