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/* GXemul: $Id: i8253reg.h,v 1.1 2006/07/18 19:48:03 debug Exp $ */ |
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/* $NetBSD: i8253reg.h,v 1.9 2005/12/11 12:21:26 christos Exp $ */ |
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#ifndef I8253REG_H |
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#define I8253REG_H |
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|
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/*- |
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* Copyright (c) 1993 The Regents of the University of California. |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. Neither the name of the University nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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*/ |
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|
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/* |
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* Register definitions for the Intel 8253 Programmable Interval Timer. |
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* |
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* This chip has three independent 16-bit down counters that can be |
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* read on the fly. There are three mode registers and three countdown |
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* registers. The countdown registers are addressed directly, via the |
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* first three I/O ports. The three mode registers are accessed via |
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* the fourth I/O port, with two bits in the mode byte indicating the |
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* register. (Why are hardware interfaces always so braindead?). |
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* |
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* To write a value into the countdown register, the mode register |
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* is first programmed with a command indicating the which byte of |
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* the two byte register is to be modified. The three possibilities |
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* are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then |
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* msb (TMR_MR_BOTH). |
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* |
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* To read the current value ("on the fly") from the countdown register, |
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* you write a "latch" command into the mode register, then read the stable |
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* value from the corresponding I/O port. For example, you write |
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* TMR_MR_LATCH into the corresponding mode register. Presumably, |
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* after doing this, a write operation to the I/O port would result |
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* in undefined behavior (but hopefully not fry the chip). |
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* Reading in this manner has no side effects. |
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* |
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* The outputs of the three timers are connected as follows: |
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* |
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* timer 0 -> irq 0 |
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* timer 1 -> DMA chan 0 (for dram refresh) |
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* timer 2 -> speaker (via keyboard controller) |
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* |
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* Timer 0 is used to call hardclock. |
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* Timer 2 is used to generate console beeps. |
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*/ |
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|
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/* |
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* Frequency of all three count-down timers; (I8253_TIMER_FREQ/freq) is the |
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* appropriate count to generate a frequency of freq Hz. |
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*/ |
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#ifndef I8253_TIMER_FREQ |
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#define I8253_TIMER_FREQ 1193182 |
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#endif |
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#define I8253_TIMER_DIV(x) ((I8253_TIMER_FREQ+(x)/2)/(x)) |
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|
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/* |
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* Macros for specifying values to be written into a mode register. |
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*/ |
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#define I8253_TIMER_CNTR0 0 /* timer 0 counter port */ |
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#define I8253_TIMER_CNTR1 1 /* timer 1 counter port */ |
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#define I8253_TIMER_CNTR2 2 /* timer 2 counter port */ |
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#define I8253_TIMER_MODE 3 /* timer mode port */ |
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#define I8253_TIMER_SEL0 0x00 /* select counter 0 */ |
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#define I8253_TIMER_SEL1 0x40 /* select counter 1 */ |
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#define I8253_TIMER_SEL2 0x80 /* select counter 2 */ |
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#define I8253_TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */ |
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#define I8253_TIMER_ONESHOT 0x02 /* mode 1, one shot */ |
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#define I8253_TIMER_RATEGEN 0x04 /* mode 2, rate generator */ |
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#define I8253_TIMER_SQWAVE 0x06 /* mode 3, square wave */ |
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#define I8253_TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */ |
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#define I8253_TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */ |
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#define I8253_TIMER_LATCH 0x00 /* latch counter for reading */ |
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#define I8253_TIMER_LSB 0x10 /* r/w counter LSB */ |
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#define I8253_TIMER_MSB 0x20 /* r/w counter MSB */ |
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#define I8253_TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */ |
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#define I8253_TIMER_BCD 0x01 /* count in BCD */ |
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|
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#endif /* I8253REG_H */ |
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