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dpavlin |
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/* GXemul: $Id: i80321reg.h,v 1.1 2005/10/17 05:32:21 debug Exp $ */ |
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/* $NetBSD: i80321reg.h,v 1.14 2003/12/19 10:08:11 gavan Exp $ */ |
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/* |
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* Copyright (c) 2002 Wasabi Systems, Inc. |
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* All rights reserved. |
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* |
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* Written by Jason R. Thorpe for Wasabi Systems, Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed for the NetBSD Project by |
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* Wasabi Systems, Inc. |
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse |
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* or promote products derived from this software without specific prior |
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* written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#ifndef _ARM_XSCALE_I80321REG_H_ |
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#define _ARM_XSCALE_I80321REG_H_ |
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/* |
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* Register definitions for the Intel 80321 (``Verde'') I/O processor, |
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* based on the XScale core. |
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*/ |
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/* |
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* Base i80321 memory map: |
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* |
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* 0x0000.0000 - 0x7fff.ffff ATU Outbound Direct Addressing Window |
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* 0x8000.0000 - 0x9001.ffff ATU Outbound Translation Windows |
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* 0x9002.0000 - 0xffff.dfff External Memory |
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* 0xffff.e000 - 0xffff.e8ff Peripheral Memory Mapped Registers |
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* 0xffff.e900 - 0xffff.ffff Reserved |
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*/ |
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#define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL |
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#define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL |
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#define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL |
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#define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL |
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#define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL |
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#define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL |
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#define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL |
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#define VERDE_EXTMEM_BASE 0x90020000UL |
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#define VERDE_PMMR_BASE 0xffffe000UL |
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#define VERDE_PMMR_SIZE 0x00001700UL |
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/* |
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* Peripheral Memory Mapped Registers. Defined as offsets |
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* from the VERDE_PMMR_BASE. |
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*/ |
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#define VERDE_ATU_BASE 0x0100 |
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#define VERDE_ATU_SIZE 0x0100 |
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#define VERDE_MU_BASE 0x0300 |
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#define VERDE_MU_SIZE 0x0100 |
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#define VERDE_DMA_BASE 0x0400 |
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#define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00) |
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#define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40) |
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#define VERDE_DMA_SIZE 0x0100 |
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#define VERDE_DMA_CHSIZE 0x0040 |
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#define VERDE_MCU_BASE 0x0500 |
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#define VERDE_MCU_SIZE 0x0100 |
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#define VERDE_SSP_BASE 0x0600 |
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#define VERDE_SSP_SIZE 0x0080 |
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#define VERDE_PBIU_BASE 0x0680 |
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#define VERDE_PBIU_SIZE 0x0080 |
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#define VERDE_AAU_BASE 0x0800 |
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#define VERDE_AAU_SIZE 0x0100 |
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#define VERDE_I2C_BASE 0x1680 |
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#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) |
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#define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) |
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#define VERDE_I2C_SIZE 0x0080 |
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#define VERDE_I2C_CHSIZE 0x0020 |
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/* |
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* Address Translation Unit |
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*/ |
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/* 0x00 - 0x38 -- PCI configuration space header */ |
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#define ATU_IALR0 0x40 /* Inbound ATU Limit 0 */ |
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#define ATU_IATVR0 0x44 /* Inbound ATU Xlate Value 0 */ |
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#define ATU_ERLR 0x48 /* Expansion ROM Limit */ |
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#define ATU_ERTVR 0x4c /* Expansion ROM Xlate Value */ |
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#define ATU_IALR1 0x50 /* Inbound ATU Limit 1 */ |
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#define ATU_IALR2 0x54 /* Inbound ATU Limit 2 */ |
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#define ATU_IATVR2 0x58 /* Inbound ATU Xlate Value 2 */ |
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#define ATU_OIOWTVR 0x5c /* Outbound I/O Window Xlate Value */ |
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#define ATU_OMWTVR0 0x60 /* Outbound Mem Window Xlate Value 0 */ |
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#define ATU_OUMWTVR0 0x64 /* Outbound Mem Window Xlate Value 0 Upper */ |
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#define ATU_OMWTVR1 0x68 /* Outbound Mem Window Xlate Value 1 */ |
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#define ATU_OUMWTVR1 0x6c /* Outbound Mem Window Xlate Value 1 Upper */ |
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#define ATU_OUDWTVR 0x78 /* Outbound Mem Direct Xlate Value Upper */ |
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#define ATU_ATUCR 0x80 /* ATU Configuration */ |
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#define ATU_PCSR 0x84 /* PCI Configuration and Status */ |
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#define ATU_ATUISR 0x88 /* ATU Interrupt Status */ |
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#define ATU_ATUIMR 0x8c /* ATU Interrupt Mask */ |
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#define ATU_IABAR3 0x90 /* Inbound ATU Base Address 3 */ |
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#define ATU_IAUBAR3 0x94 /* Inbound ATU Base Address 3 Upper */ |
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#define ATU_IALR3 0x98 /* Inbound ATU Limit 3 */ |
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#define ATU_IATVR3 0x9c /* Inbound ATU Xlate Value 3 */ |
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#define ATU_OCCAR 0xa4 /* Outbound Configuration Cycle Address */ |
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#define ATU_OCCDR 0xac /* Outbound Configuration Cycle Data */ |
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#define ATU_MSI_PORT 0xb4 /* MSI port */ |
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#define ATU_PDSCR 0xbc /* PCI Bus Drive Strength Control */ |
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#define ATU_PCI_X_CAP_ID 0xe0 /* (1) */ |
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#define ATU_PCI_X_NEXT 0xe1 /* (1) */ |
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#define ATU_PCIXCMD 0xe2 /* PCI-X Command Register (2) */ |
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#define ATU_PCIXSR 0xe4 /* PCI-X Status Register */ |
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#define ATUCR_DRC_ALIAS (1U << 19) |
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#define ATUCR_DAU2GXEN (1U << 18) |
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#define ATUCR_P_SERR_MA (1U << 16) |
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#define ATUCR_DTS (1U << 15) |
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#define ATUCR_P_SERR_DIE (1U << 9) |
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#define ATUCR_DAE (1U << 8) |
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#define ATUCR_BIST_IE (1U << 3) |
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#define ATUCR_OUT_EN (1U << 1) |
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#define PCSR_DAAAPE (1U << 18) |
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#define PCSR_PCI_X_CAP (3U << 16) |
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#define PCSR_PCI_X_CAP_BORING (0 << 16) |
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#define PCSR_PCI_X_CAP_66 (1U << 16) |
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#define PCSR_PCI_X_CAP_100 (2U << 16) |
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#define PCSR_PCI_X_CAP_133 (3U << 16) |
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#define PCSR_OTQB (1U << 15) |
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#define PCSR_IRTQB (1U << 14) |
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#define PCSR_DTV (1U << 12) |
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#define PCSR_BUS66 (1U << 10) |
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#define PCSR_BUS64 (1U << 8) |
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#define PCSR_RIB (1U << 5) |
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#define PCSR_RPB (1U << 4) |
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#define PCSR_CCR (1U << 2) |
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#define PCSR_CPR (1U << 1) |
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#define ATUISR_IMW1BU (1U << 14) |
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#define ATUISR_ISCEM (1U << 13) |
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#define ATUISR_RSCEM (1U << 12) |
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#define ATUISR_PST (1U << 11) |
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#define ATUISR_P_SERR_ASRT (1U << 10) |
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#define ATUISR_DPE (1U << 9) |
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#define ATUISR_BIST (1U << 8) |
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#define ATUISR_IBMA (1U << 7) |
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#define ATUISR_P_SERR_DET (1U << 4) |
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#define ATUISR_PMA (1U << 3) |
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#define ATUISR_PTAM (1U << 2) |
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#define ATUISR_PTAT (1U << 1) |
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#define ATUISR_PMPE (1U << 0) |
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#define ATUIMR_IMW1BU (1U << 11) |
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#define ATUIMR_ISCEM (1U << 10) |
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#define ATUIMR_RSCEM (1U << 9) |
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#define ATUIMR_PST (1U << 8) |
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#define ATUIMR_DPE (1U << 7) |
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#define ATUIMR_P_SERR_ASRT (1U << 6) |
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#define ATUIMR_PMA (1U << 5) |
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#define ATUIMR_PTAM (1U << 4) |
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#define ATUIMR_PTAT (1U << 3) |
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#define ATUIMR_PMPE (1U << 2) |
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#define ATUIMR_IE_SERR_EN (1U << 1) |
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#define ATUIMR_ECC_TAE (1U << 0) |
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#define PCIXCMD_MOST_1 (0 << 4) |
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#define PCIXCMD_MOST_2 (1 << 4) |
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#define PCIXCMD_MOST_3 (2 << 4) |
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#define PCIXCMD_MOST_4 (3 << 4) |
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#define PCIXCMD_MOST_8 (4 << 4) |
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#define PCIXCMD_MOST_12 (5 << 4) |
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#define PCIXCMD_MOST_16 (6 << 4) |
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#define PCIXCMD_MOST_32 (7 << 4) |
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#define PCIXCMD_MOST_MASK (7 << 4) |
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#define PCIXCMD_MMRBC_512 (0 << 2) |
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#define PCIXCMD_MMRBC_1024 (1 << 2) |
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#define PCIXCMD_MMRBC_2048 (2 << 2) |
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#define PCIXCMD_MMRBC_4096 (3 << 2) |
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#define PCIXCMD_MMRBC_MASK (3 << 2) |
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#define PCIXCMD_ERO (1U << 1) |
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#define PCIXCMD_DPERE (1U << 0) |
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#define PCIXSR_RSCEM (1U << 29) |
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#define PCIXSR_DMCRS_MASK (7 << 26) |
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#define PCIXSR_DMOST_MASK (7 << 23) |
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#define PCIXSR_COMPLEX (1U << 20) |
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#define PCIXSR_USC (1U << 19) |
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#define PCIXSR_SCD (1U << 18) |
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#define PCIXSR_133_CAP (1U << 17) |
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#define PCIXSR_32PCI (1U << 16) /* 0 = 32, 1 = 64 */ |
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#define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) |
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#define PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3) |
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#define PCIXSR_FUNCNO(x) ((x) & 0x7) |
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/* |
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* Memory Controller Unit |
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*/ |
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#define MCU_SDIR 0x00 /* DDR SDRAM Init. Register */ |
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#define MCU_SDCR 0x04 /* DDR SDRAM Control Register */ |
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#define MCU_SDBR 0x08 /* SDRAM Base Register */ |
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#define MCU_SBR0 0x0c /* SDRAM Boundary 0 */ |
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#define MCU_SBR1 0x10 /* SDRAM Boundary 1 */ |
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#define MCU_ECCR 0x34 /* ECC Control Register */ |
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#define MCU_ELOG0 0x38 /* ECC Log 0 */ |
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#define MCU_ELOG1 0x3c /* ECC Log 1 */ |
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#define MCU_ECAR0 0x40 /* ECC address 0 */ |
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#define MCU_ECAR1 0x44 /* ECC address 1 */ |
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#define MCU_ECTST 0x48 /* ECC test register */ |
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#define MCU_MCISR 0x4c /* MCU Interrupt Status Register */ |
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#define MCU_RFR 0x50 /* Refresh Frequency Register */ |
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#define MCU_DBUDSR 0x54 /* Data Bus Pull-up Drive Strength */ |
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#define MCU_DBDDSR 0x58 /* Data Bus Pull-down Drive Strength */ |
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#define MCU_CUDSR 0x5c /* Clock Pull-up Drive Strength */ |
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#define MCU_CDDSR 0x60 /* Clock Pull-down Drive Strength */ |
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#define MCU_CEUDSR 0x64 /* Clock En Pull-up Drive Strength */ |
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#define MCU_CEDDSR 0x68 /* Clock En Pull-down Drive Strength */ |
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#define MCU_CSUDSR 0x6c /* Chip Sel Pull-up Drive Strength */ |
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#define MCU_CSDDSR 0x70 /* Chip Sel Pull-down Drive Strength */ |
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#define MCU_REUDSR 0x74 /* Rx En Pull-up Drive Strength */ |
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#define MCU_REDDSR 0x78 /* Rx En Pull-down Drive Strength */ |
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#define MCU_ABUDSR 0x7c /* Addr Bus Pull-up Drive Strength */ |
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#define MCU_ABDDSR 0x80 /* Addr Bus Pull-down Drive Strength */ |
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#define MCU_DSDR 0x84 /* Data Strobe Delay Register */ |
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#define MCU_REDR 0x88 /* Rx Enable Delay Register */ |
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#define SDCR_DIMMTYPE (1U << 1) /* 0 = unbuf, 1 = reg */ |
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#define SDCR_BUSWIDTH (1U << 2) /* 0 = 64, 1 = 32 */ |
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#define SBRx_TECH (1U << 31) |
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#define SBRx_BOUND 0x0000003f |
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#define ECCR_SBERE (1U << 0) |
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#define ECCR_MBERE (1U << 1) |
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#define ECCR_SBECE (1U << 2) |
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#define ECCR_ECCEN (1U << 3) |
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#define ELOGx_SYNDROME 0x000000ff |
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#define ELOGx_ERRTYPE (1U << 8) /* 1 = multi-bit */ |
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#define ELOGx_RW (1U << 12) /* 1 = write error */ |
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/* |
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* Dev ID Func Requester |
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* 2 0 XScale core |
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* 2 1 ATU |
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* 13 0 DMA channel 0 |
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* 13 1 DMA channel 1 |
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* 26 0 ATU |
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*/ |
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#define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) |
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#define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) |
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#define MCISR_ECC_ERR0 (1U << 0) |
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#define MCISR_ECC_ERR1 (1U << 1) |
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#define MCISR_ECC_ERRN (1U << 2) |
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/* |
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* Timers |
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* |
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* The i80321 timer registers are available in both memory-mapped |
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* and coprocessor spaces. Most of the registers are read-only |
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* if memory-mapped, so we access them via coprocessor space. |
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* |
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* TMR0 cp6 c0,1 0xffffe7e0 |
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* TMR1 cp6 c1,1 0xffffe7e4 |
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* TCR0 cp6 c2,1 0xffffe7e8 |
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* TCR1 cp6 c3,1 0xffffe7ec |
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* TRR0 cp6 c4,1 0xffffe7f0 |
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* TRR1 cp6 c5,1 0xffffe7f4 |
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* TISR cp6 c6,1 0xffffe7f8 |
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* WDTCR cp6 c7,1 0xffffe7fc |
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*/ |
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#define TMRx_TC (1U << 0) |
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#define TMRx_ENABLE (1U << 1) |
| 301 |
|
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#define TMRx_RELOAD (1U << 2) |
| 302 |
|
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#define TMRx_CSEL_CORE (0 << 4) |
| 303 |
|
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#define TMRx_CSEL_CORE_div4 (1 << 4) |
| 304 |
|
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#define TMRx_CSEL_CORE_div8 (2 << 4) |
| 305 |
|
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#define TMRx_CSEL_CORE_div16 (3 << 4) |
| 306 |
|
|
|
| 307 |
|
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#define TISR_TMR0 (1U << 0) |
| 308 |
|
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#define TISR_TMR1 (1U << 1) |
| 309 |
|
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|
| 310 |
|
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#define WDTCR_ENABLE1 0x1e1e1e1e |
| 311 |
|
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#define WDTCR_ENABLE2 0xe1e1e1e1 |
| 312 |
|
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| 313 |
|
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/* |
| 314 |
|
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* Interrupt Controller Unit. |
| 315 |
|
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* |
| 316 |
|
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* INTCTL cp6 c0,0 0xffffe7d0 |
| 317 |
|
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* INTSTR cp6 c4,0 0xffffe7d4 |
| 318 |
|
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* IINTSRC cp6 c8,0 0xffffe7d8 |
| 319 |
|
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* FINTSRC cp6 c9,0 0xffffe7dc |
| 320 |
|
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* PIRSR 0xffffe1ec |
| 321 |
|
|
*/ |
| 322 |
|
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| 323 |
|
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#define ICU_PIRSR 0x01ec |
| 324 |
|
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#define ICU_GPOE 0x07c4 |
| 325 |
|
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#define ICU_GPID 0x07c8 |
| 326 |
|
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#define ICU_GPOD 0x07cc |
| 327 |
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|
| 328 |
|
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/* |
| 329 |
|
|
* NOTE: WE USE THE `bitXX' BITS TO INDICATE PENDING SOFTWARE |
| 330 |
|
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* INTERRUPTS. See i80321_icu.c |
| 331 |
|
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*/ |
| 332 |
|
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#define ICU_INT_HPI 31 /* high priority interrupt */ |
| 333 |
|
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#define ICU_INT_XINT0 27 /* external interrupts */ |
| 334 |
|
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#define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) |
| 335 |
|
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#define ICU_INT_bit26 26 |
| 336 |
|
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#define ICU_INT_SSP 25 /* SSP serial port */ |
| 337 |
|
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#define ICU_INT_MUE 24 /* msg unit error */ |
| 338 |
|
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#define ICU_INT_AAUE 23 /* AAU error */ |
| 339 |
|
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#define ICU_INT_bit22 22 |
| 340 |
|
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#define ICU_INT_DMA1E 21 /* DMA Ch 1 error */ |
| 341 |
|
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#define ICU_INT_DMA0E 20 /* DMA Ch 0 error */ |
| 342 |
|
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#define ICU_INT_MCUE 19 /* memory controller error */ |
| 343 |
|
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#define ICU_INT_ATUE 18 /* ATU error */ |
| 344 |
|
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#define ICU_INT_BIUE 17 /* bus interface unit error */ |
| 345 |
|
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#define ICU_INT_PMU 16 /* XScale PMU */ |
| 346 |
|
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#define ICU_INT_PPM 15 /* peripheral PMU */ |
| 347 |
|
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#define ICU_INT_BIST 14 /* ATU Start BIST */ |
| 348 |
|
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#define ICU_INT_MU 13 /* messaging unit */ |
| 349 |
|
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#define ICU_INT_I2C1 12 /* i2c unit 1 */ |
| 350 |
|
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#define ICU_INT_I2C0 11 /* i2c unit 0 */ |
| 351 |
|
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#define ICU_INT_TMR1 10 /* timer 1 */ |
| 352 |
|
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#define ICU_INT_TMR0 9 /* timer 0 */ |
| 353 |
|
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#define ICU_INT_CPPM 8 /* core processor PMU */ |
| 354 |
|
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#define ICU_INT_AAU_EOC 7 /* AAU end-of-chain */ |
| 355 |
|
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#define ICU_INT_AAU_EOT 6 /* AAU end-of-transfer */ |
| 356 |
|
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#define ICU_INT_bit5 5 |
| 357 |
|
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#define ICU_INT_bit4 4 |
| 358 |
|
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#define ICU_INT_DMA1_EOC 3 /* DMA1 end-of-chain */ |
| 359 |
|
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#define ICU_INT_DMA1_EOT 2 /* DMA1 end-of-transfer */ |
| 360 |
|
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#define ICU_INT_DMA0_EOC 1 /* DMA0 end-of-chain */ |
| 361 |
|
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#define ICU_INT_DMA0_EOT 0 /* DMA0 end-of-transfer */ |
| 362 |
|
|
|
| 363 |
|
|
#define ICU_INT_HWMASK (0xffffffff & \ |
| 364 |
|
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~((1 << ICU_INT_bit26) | \ |
| 365 |
|
|
(1 << ICU_INT_bit22) | \ |
| 366 |
|
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(1 << ICU_INT_bit5) | \ |
| 367 |
|
|
(1 << ICU_INT_bit4))) |
| 368 |
|
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|
| 369 |
|
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/* |
| 370 |
|
|
* SSP Serial Port |
| 371 |
|
|
*/ |
| 372 |
|
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|
| 373 |
|
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#define SSP_SSCR0 0x00 /* SSC control 0 */ |
| 374 |
|
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#define SSP_SSCR1 0x04 /* SSC control 1 */ |
| 375 |
|
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#define SSP_SSSR 0x08 /* SSP status */ |
| 376 |
|
|
#define SSP_SSITR 0x0c /* SSP interrupt test */ |
| 377 |
|
|
#define SSP_SSDR 0x10 /* SSP data */ |
| 378 |
|
|
|
| 379 |
|
|
#define SSP_SSCR0_DSIZE(x) ((x) - 1)/* data size: 4..16 */ |
| 380 |
|
|
#define SSP_SSCR0_FRF_SPI (0 << 4) /* Motorola Serial Periph Iface */ |
| 381 |
|
|
#define SSP_SSCR0_FRF_SSP (1U << 4)/* TI Sync. Serial Protocol */ |
| 382 |
|
|
#define SSP_SSCR0_FRF_UWIRE (2U << 4)/* NatSemi Microwire */ |
| 383 |
|
|
#define SSP_SSCR0_FRF_rsvd (3U << 4)/* reserved */ |
| 384 |
|
|
#define SSP_SSCR0_ECS (1U << 6)/* external clock select */ |
| 385 |
|
|
#define SSP_SSCR0_SSE (1U << 7)/* sync. serial port enable */ |
| 386 |
|
|
#define SSP_SSCR0_SCR(x) ((x) << 8)/* serial clock rate */ |
| 387 |
|
|
/* bit rate = 3.6864 * 10e6 / |
| 388 |
|
|
(2 * (SCR + 1)) */ |
| 389 |
|
|
|
| 390 |
|
|
#define SSP_SSCR1_RIE (1U << 0)/* Rx FIFO interrupt enable */ |
| 391 |
|
|
#define SSP_SSCR1_TIE (1U << 1)/* Tx FIFO interrupt enable */ |
| 392 |
|
|
#define SSP_SSCR1_LBM (1U << 2)/* loopback mode enable */ |
| 393 |
|
|
#define SSP_SSCR1_SPO (1U << 3)/* Moto SPI SSCLK pol. (1 = high) */ |
| 394 |
|
|
#define SSP_SSCR1_SPH (1U << 4)/* Moto SPI SSCLK phase: |
| 395 |
|
|
0 = inactive full at start, |
| 396 |
|
|
1/2 at end of frame |
| 397 |
|
|
1 = inactive 1/2 at start, |
| 398 |
|
|
full at end of frame */ |
| 399 |
|
|
#define SSP_SSCR1_MWDS (1U << 5)/* Microwire data size: |
| 400 |
|
|
0 = 8 bit |
| 401 |
|
|
1 = 16 bit */ |
| 402 |
|
|
#define SSP_SSCR1_TFT (((x) - 1) << 6) /* Tx FIFO threshold */ |
| 403 |
|
|
#define SSP_SSCR1_RFT (((x) - 1) << 10)/* Rx FIFO threshold */ |
| 404 |
|
|
#define SSP_SSCR1_EFWR (1U << 14)/* enab. FIFO write/read */ |
| 405 |
|
|
#define SSP_SSCR1_STRF (1U << 15)/* FIFO write/read FIFO select: |
| 406 |
|
|
0 = Tx FIFO |
| 407 |
|
|
1 = Rx FIFO */ |
| 408 |
|
|
|
| 409 |
|
|
#define SSP_SSSR_TNF (1U << 2)/* Tx FIFO not full */ |
| 410 |
|
|
#define SSP_SSSR_RNE (1U << 3)/* Rx FIFO not empty */ |
| 411 |
|
|
#define SSP_SSSR_BSY (1U << 4)/* SSP is busy */ |
| 412 |
|
|
#define SSP_SSSR_TFS (1U << 5)/* Tx FIFO service request */ |
| 413 |
|
|
#define SSP_SSSR_RFS (1U << 6)/* Rx FIFO service request */ |
| 414 |
|
|
#define SSP_SSSR_ROR (1U << 7)/* Rx FIFO overrun */ |
| 415 |
|
|
#define SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) /* Tx FIFO level */ |
| 416 |
|
|
#define SSP_SSSR_RFL(x) (((x) >> 12) & 0xf)/* Rx FIFO level */ |
| 417 |
|
|
|
| 418 |
|
|
#define SSP_SSITR_TTFS (1U << 5)/* Test Tx FIFO service */ |
| 419 |
|
|
#define SSP_SSITR_TRFS (1U << 6)/* Test Rx FIFO service */ |
| 420 |
|
|
#define SSP_SSITR_TROR (1U << 7)/* Test Rx overrun */ |
| 421 |
|
|
|
| 422 |
|
|
/* |
| 423 |
|
|
* Peripheral Bus Interface Unit |
| 424 |
|
|
*/ |
| 425 |
|
|
|
| 426 |
|
|
#define PBIU_PBCR 0x00 /* PBIU Control Register */ |
| 427 |
|
|
#define PBIU_PBBAR0 0x08 /* PBIU Base Address Register 0 */ |
| 428 |
|
|
#define PBIU_PBLR0 0x0c /* PBIU Limit Register 0 */ |
| 429 |
|
|
#define PBIU_PBBAR1 0x10 /* PBIU Base Address Register 1 */ |
| 430 |
|
|
#define PBIU_PBLR1 0x14 /* PBIU Limit Register 1 */ |
| 431 |
|
|
#define PBIU_PBBAR2 0x18 /* PBIU Base Address Register 2 */ |
| 432 |
|
|
#define PBIU_PBLR2 0x1c /* PBIU Limit Register 2 */ |
| 433 |
|
|
#define PBIU_PBBAR3 0x20 /* PBIU Base Address Register 3 */ |
| 434 |
|
|
#define PBIU_PBLR3 0x24 /* PBIU Limit Register 3 */ |
| 435 |
|
|
#define PBIU_PBBAR4 0x28 /* PBIU Base Address Register 4 */ |
| 436 |
|
|
#define PBIU_PBLR4 0x2c /* PBIU Limit Register 4 */ |
| 437 |
|
|
#define PBIU_PBBAR5 0x30 /* PBIU Base Address Register 5 */ |
| 438 |
|
|
#define PBIU_PBLR5 0x34 /* PBIU Limit Register 5 */ |
| 439 |
|
|
#define PBIU_DSCR 0x38 /* PBIU Drive Strength Control Reg. */ |
| 440 |
|
|
#define PBIU_MBR0 0x40 /* PBIU Memory-less Boot Reg. 0 */ |
| 441 |
|
|
#define PBIU_MBR1 0x60 /* PBIU Memory-less Boot Reg. 1 */ |
| 442 |
|
|
#define PBIU_MBR2 0x64 /* PBIU Memory-less Boot Reg. 2 */ |
| 443 |
|
|
|
| 444 |
|
|
#define PBIU_PBCR_PBIEN (1 << 0) |
| 445 |
|
|
#define PBIU_PBCR_PBI100 (1 << 1) |
| 446 |
|
|
#define PBIU_PBCR_PBI66 (2 << 1) |
| 447 |
|
|
#define PBIU_PBCR_PBI33 (3 << 1) |
| 448 |
|
|
#define PBIU_PBCR_PBBEN (1 << 3) |
| 449 |
|
|
|
| 450 |
|
|
#define PBIU_PBARx_WIDTH8 (0 << 0) |
| 451 |
|
|
#define PBIU_PBARx_WIDTH16 (1 << 0) |
| 452 |
|
|
#define PBIU_PBARx_WIDTH32 (2 << 0) |
| 453 |
|
|
#define PBIU_PBARx_ADWAIT4 (0 << 2) |
| 454 |
|
|
#define PBIU_PBARx_ADWAIT8 (1 << 2) |
| 455 |
|
|
#define PBIU_PBARx_ADWAIT12 (2 << 2) |
| 456 |
|
|
#define PBIU_PBARx_ADWAIT16 (3 << 2) |
| 457 |
|
|
#define PBIU_PBARx_ADWAIT20 (4 << 2) |
| 458 |
|
|
#define PBIU_PBARx_RCWAIT1 (0 << 6) |
| 459 |
|
|
#define PBIU_PBARx_RCWAIT4 (1 << 6) |
| 460 |
|
|
#define PBIU_PBARx_RCWAIT8 (2 << 6) |
| 461 |
|
|
#define PBIU_PBARx_RCWAIT12 (3 << 6) |
| 462 |
|
|
#define PBIU_PBARx_RCWAIT16 (4 << 6) |
| 463 |
|
|
#define PBIU_PBARx_RCWAIT20 (5 << 6) |
| 464 |
|
|
#define PBIU_PBARx_FWE (1 << 9) |
| 465 |
|
|
#define PBIU_BASE_MASK 0xfffff000U |
| 466 |
|
|
|
| 467 |
|
|
#define PBIU_PBLRx_SIZE(x) (~((x) - 1)) |
| 468 |
|
|
|
| 469 |
|
|
/* |
| 470 |
|
|
* Messaging Unit |
| 471 |
|
|
*/ |
| 472 |
|
|
#define MU_IMR0 0x0010 /* MU Inbound Message Register 0 */ |
| 473 |
|
|
#define MU_IMR1 0x0014 /* MU Inbound Message Register 1 */ |
| 474 |
|
|
#define MU_OMR0 0x0018 /* MU Outbound Message Register 0 */ |
| 475 |
|
|
#define MU_OMR1 0x001c /* MU Outbound Message Register 1 */ |
| 476 |
|
|
#define MU_IDR 0x0020 /* MU Inbound Doorbell Register */ |
| 477 |
|
|
#define MU_IISR 0x0024 /* MU Inbound Interrupt Status Reg */ |
| 478 |
|
|
#define MU_IIMR 0x0028 /* MU Inbound Interrupt Mask Reg */ |
| 479 |
|
|
#define MU_ODR 0x002c /* MU Outbound Doorbell Register */ |
| 480 |
|
|
#define MU_OISR 0x0030 /* MU Outbound Interrupt Status Reg */ |
| 481 |
|
|
#define MU_OIMR 0x0034 /* MU Outbound Interrupt Mask Reg */ |
| 482 |
|
|
#define MU_MUCR 0x0050 /* MU Configuration Register */ |
| 483 |
|
|
#define MU_QBAR 0x0054 /* MU Queue Base Address Register */ |
| 484 |
|
|
#define MU_IFHPR 0x0060 /* MU Inbound Free Head Pointer Reg */ |
| 485 |
|
|
#define MU_IFTPR 0x0064 /* MU Inbound Free Tail Pointer Reg */ |
| 486 |
|
|
#define MU_IPHPR 0x0068 /* MU Inbound Post Head Pointer Reg */ |
| 487 |
|
|
#define MU_IPTPR 0x006c /* MU Inbound Post Tail Pointer Reg */ |
| 488 |
|
|
#define MU_OFHPR 0x0070 /* MU Outbound Free Head Pointer Reg */ |
| 489 |
|
|
#define MU_OFTPR 0x0074 /* MU Outbound Free Tail Pointer Reg */ |
| 490 |
|
|
#define MU_OPHPR 0x0078 /* MU Outbound Post Head Pointer Reg */ |
| 491 |
|
|
#define MU_OPTPR 0x007c /* MU Outbound Post Tail Pointer Reg */ |
| 492 |
|
|
#define MU_IAR 0x0080 /* MU Index Address Register */ |
| 493 |
|
|
|
| 494 |
|
|
#define MU_IIMR_IRI (1 << 6) /* Index Register Interrupt */ |
| 495 |
|
|
#define MU_IIMR_OFQFI (1 << 5) /* Outbound Free Queue Full Int. */ |
| 496 |
|
|
#define MU_IIMR_IPQI (1 << 4) /* Inbound Post Queue Interrupt */ |
| 497 |
|
|
#define MU_IIMR_EDI (1 << 3) /* Error Doorbell Interrupt */ |
| 498 |
|
|
#define MU_IIMR_IDI (1 << 2) /* Inbound Doorbell Interrupt */ |
| 499 |
|
|
#define MU_IIMR_IM1I (1 << 1) /* Inbound Message 1 Interrupt */ |
| 500 |
|
|
#define MU_IIMR_IM0I (1 << 0) /* Inbound Message 0 Interrupt */ |
| 501 |
|
|
|
| 502 |
|
|
#endif /* _ARM_XSCALE_I80321REG_H_ */ |
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