src/include/ee_timerreg.h

/*  gxemul: $Id: ee_timerreg.h,v 1.3 2005/03/05 12:34:02 debug Exp $  */
/*      $NetBSD: timerreg.h,v 1.1 2001/10/16 15:38:40 uch Exp $ */

/*-
 * Copyright (c) 2001 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by UCHIYAMA Yasushi.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *        This product includes software developed by the NetBSD
 *        Foundation, Inc. and its contributors.
 * 4. Neither the name of The NetBSD Foundation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * 16bit timer 0:3
 *      source: BUSCLK, H-BLNK
 */

#define EE_TIMER_MIN            0
#define EE_TIMER_MAX            3
#define LEGAL_TIMER(x)                                                  \
        (((x) >= EE_TIMER_MIN) && ((x) <= EE_TIMER_MAX))

/* Register address. all registers are 32bit wide */
#define TIMER_REGBASE           0x10000000
#define TIMER_REGSIZE           0x2000
#define TIMER_OFS               0x800

#define T_COUNT_REG(x)  MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + TIMER_OFS * (x)))
#define T_MODE_REG(x)   MIPS_PHYS_TO_KSEG1((TIMER_REGBASE +             \
        TIMER_OFS * (x) + 0x10))
#define T_COMP_REG(x)   MIPS_PHYS_TO_KSEG1((TIMER_REGBASE +             \
        TIMER_OFS * (x) + 0x20))
/* 
 * timer0, timer1 have `hold register'. 
 * (save T_COUNT when SBUS interrupt occured)
 */
#define T_HOLD_REG(x)   (TIMER_REGBASE + TIMER_OFS * (x) + 0x30)

#define T0_COUNT_REG            MIPS_PHYS_TO_KSEG1(0x10000000)
#define T0_MODE_REG             MIPS_PHYS_TO_KSEG1(0x10000010)
#define T0_COMP_REG             MIPS_PHYS_TO_KSEG1(0x10000020)
#define T0_HOLD_REG             MIPS_PHYS_TO_KSEG1(0x10000030)
#define T1_COUNT_REG            MIPS_PHYS_TO_KSEG1(0x10000800)
#define T1_MODE_REG             MIPS_PHYS_TO_KSEG1(0x10000810)
#define T1_COMP_REG             MIPS_PHYS_TO_KSEG1(0x10000820)
#define T1_HOLD_REG             MIPS_PHYS_TO_KSEG1(0x10000830)
#define T2_COUNT_REG            MIPS_PHYS_TO_KSEG1(0x10001000)
#define T2_MODE_REG             MIPS_PHYS_TO_KSEG1(0x10001010)
#define T2_COMP_REG             MIPS_PHYS_TO_KSEG1(0x10001020)
#define T3_COUNT_REG            MIPS_PHYS_TO_KSEG1(0x10001800)
#define T3_MODE_REG             MIPS_PHYS_TO_KSEG1(0x10001810)
#define T3_COMP_REG             MIPS_PHYS_TO_KSEG1(0x10001820)

/*
 * Tn_MODE: mode, status register.
 */
#define T_MODE_CLKS_MASK                0x3
#define T_MODE_CLKS(x)          ((x) & T_MODE_CLKS_MASK)
#define T_MODE_CLKS_CLR(x)      ((x) & ~T_MODE_CLKS_MASK)

#define T_MODE_CLKS_BUSCLK1             0       /* 150Mhz */
#define T_MODE_CLKS_BUSCLK16            1       /* 150 / 16 */
#define T_MODE_CLKS_BUSCLK256           2       /* 150 / 256 */
#define T_MODE_CLKS_HBLNK               3       /* H-Blank */

/* Gate Function Enabled */
#define T_MODE_GATE                     0x00000004
/* Gate Selection */
#define T_MODE_GATS_VBLNK               0x00000008
/* Gate Mode */
#define T_MODE_GATM_MASK                0x3
#define T_MODE_GATM_SHIFT               4
#define T_MODE_GATM(x)          (((x) >> T_MODE_GATM_SHIFT) & T_MODE_GATM_MASK)
#define T_MODE_GATM_CLR(x)                                              \
        ((x) & ~(T_MODE_GATM_MASK << T_MODE_GATM_SHIFT))
#define T_MODE_GATM_SET(x, val)                                         \
        ((x) | (((val) << T_MODE_GATM_SHIFT) &                          \
        (T_MODE_GATM_MASK << T_MODE_GATM_SHIFT)))
#define T_MODE_GATM_LOW                 0x0
#define T_MODE_GATM_POSEDGE             0x1
#define T_MODE_GATM_NEGEDGE             0x2
#define T_MODE_GATM_EDGE                0x3

/* Zero Return */
#define T_MODE_ZRET                     0x00000040
/* Count Up Enable */
#define T_MODE_CUE                      0x00000080
/* Compare-Interrupt Enable */
#define T_MODE_CMPE                     0x00000100
/* Overflow-Interrupt Enable */
#define T_MODE_OVFE                     0x00000200
/* Equal Flag (write clear) */
#define T_MODE_EQUF                     0x00000400
/* Overflow Flag (write clear) */
#define T_MODE_OVFF                     0x00000800

/*
 * Tn_COUNT: counter register
 */
#define T_COUNT_MASK                    0x0000ffff
#define T_COUNT(x)                      ((x) & T_COUNT_MASK)

/*
 * Tn_COMP: compare register
 */
#define T_COMP_MASK                     0x0000ffff
#define T_COMP(x)                       ((x) & T_COMP_MASK)

/*
 * Tn_HOLD: hold register
 */
#define T_HOLD_MASK                     0x0000ffff
#define T_HOLD(x)                       ((x) & T_HOLD_MASK)
1	dpavlin	4	/* gxemul: $Id: ee_timerreg.h,v 1.3 2005/03/05 12:34:02 debug Exp $ */
2			/* $NetBSD: timerreg.h,v 1.1 2001/10/16 15:38:40 uch Exp $ */
3
4			/*-
5			* Copyright (c) 2001 The NetBSD Foundation, Inc.
6			* All rights reserved.
7			*
8			* This code is derived from software contributed to The NetBSD Foundation
9			* by UCHIYAMA Yasushi.
10			*
11			* Redistribution and use in source and binary forms, with or without
12			* modification, are permitted provided that the following conditions
13			* are met:
14			* 1. Redistributions of source code must retain the above copyright
15			* notice, this list of conditions and the following disclaimer.
16			* 2. Redistributions in binary form must reproduce the above copyright
17			* notice, this list of conditions and the following disclaimer in the
18			* documentation and/or other materials provided with the distribution.
19			* 3. All advertising materials mentioning features or use of this software
20			* must display the following acknowledgement:
21			* This product includes software developed by the NetBSD
22			* Foundation, Inc. and its contributors.
23			* 4. Neither the name of The NetBSD Foundation nor the names of its
24			* contributors may be used to endorse or promote products derived
25			* from this software without specific prior written permission.
26			*
27			* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28			* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29			* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30			* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31			* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32			* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33			* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34			* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35			* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36			* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37			* POSSIBILITY OF SUCH DAMAGE.
38			*/
39
40			/*
41			* 16bit timer 0:3
42			* source: BUSCLK, H-BLNK
43			*/
44
45			#define EE_TIMER_MIN 0
46			#define EE_TIMER_MAX 3
47			#define LEGAL_TIMER(x) \
48			(((x) >= EE_TIMER_MIN) && ((x) <= EE_TIMER_MAX))
49
50			/* Register address. all registers are 32bit wide */
51			#define TIMER_REGBASE 0x10000000
52			#define TIMER_REGSIZE 0x2000
53			#define TIMER_OFS 0x800
54
55			#define T_COUNT_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + TIMER_OFS * (x)))
56			#define T_MODE_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \
57			TIMER_OFS * (x) + 0x10))
58			#define T_COMP_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \
59			TIMER_OFS * (x) + 0x20))
60			/*
61			* timer0, timer1 have `hold register'.
62			* (save T_COUNT when SBUS interrupt occured)
63			*/
64			#define T_HOLD_REG(x) (TIMER_REGBASE + TIMER_OFS * (x) + 0x30)
65
66			#define T0_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000000)
67			#define T0_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000010)
68			#define T0_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000020)
69			#define T0_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000030)
70			#define T1_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000800)
71			#define T1_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000810)
72			#define T1_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000820)
73			#define T1_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000830)
74			#define T2_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001000)
75			#define T2_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001010)
76			#define T2_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001020)
77			#define T3_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001800)
78			#define T3_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001810)
79			#define T3_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001820)
80
81			/*
82			* Tn_MODE: mode, status register.
83			*/
84			#define T_MODE_CLKS_MASK 0x3
85			#define T_MODE_CLKS(x) ((x) & T_MODE_CLKS_MASK)
86			#define T_MODE_CLKS_CLR(x) ((x) & ~T_MODE_CLKS_MASK)
87
88			#define T_MODE_CLKS_BUSCLK1 0 /* 150Mhz */
89			#define T_MODE_CLKS_BUSCLK16 1 /* 150 / 16 */
90			#define T_MODE_CLKS_BUSCLK256 2 /* 150 / 256 */
91			#define T_MODE_CLKS_HBLNK 3 /* H-Blank */
92
93			/* Gate Function Enabled */
94			#define T_MODE_GATE 0x00000004
95			/* Gate Selection */
96			#define T_MODE_GATS_VBLNK 0x00000008
97			/* Gate Mode */
98			#define T_MODE_GATM_MASK 0x3
99			#define T_MODE_GATM_SHIFT 4
100			#define T_MODE_GATM(x) (((x) >> T_MODE_GATM_SHIFT) & T_MODE_GATM_MASK)
101			#define T_MODE_GATM_CLR(x) \
102			((x) & ~(T_MODE_GATM_MASK << T_MODE_GATM_SHIFT))
103			#define T_MODE_GATM_SET(x, val) \
104			((x) \| (((val) << T_MODE_GATM_SHIFT) & \
105			(T_MODE_GATM_MASK << T_MODE_GATM_SHIFT)))
106			#define T_MODE_GATM_LOW 0x0
107			#define T_MODE_GATM_POSEDGE 0x1
108			#define T_MODE_GATM_NEGEDGE 0x2
109			#define T_MODE_GATM_EDGE 0x3
110
111			/* Zero Return */
112			#define T_MODE_ZRET 0x00000040
113			/* Count Up Enable */
114			#define T_MODE_CUE 0x00000080
115			/* Compare-Interrupt Enable */
116			#define T_MODE_CMPE 0x00000100
117			/* Overflow-Interrupt Enable */
118			#define T_MODE_OVFE 0x00000200
119			/* Equal Flag (write clear) */
120			#define T_MODE_EQUF 0x00000400
121			/* Overflow Flag (write clear) */
122			#define T_MODE_OVFF 0x00000800
123
124			/*
125			* Tn_COUNT: counter register
126			*/
127			#define T_COUNT_MASK 0x0000ffff
128			#define T_COUNT(x) ((x) & T_COUNT_MASK)
129
130			/*
131			* Tn_COMP: compare register
132			*/
133			#define T_COMP_MASK 0x0000ffff
134			#define T_COMP(x) ((x) & T_COMP_MASK)
135
136			/*
137			* Tn_HOLD: hold register
138			*/
139			#define T_HOLD_MASK 0x0000ffff
140			#define T_HOLD(x) ((x) & T_HOLD_MASK)