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/* gxemul: $Id: ee_timerreg.h,v 1.3 2005/03/05 12:34:02 debug Exp $ */ |
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/* $NetBSD: timerreg.h,v 1.1 2001/10/16 15:38:40 uch Exp $ */ |
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|
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/*- |
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* Copyright (c) 2001 The NetBSD Foundation, Inc. |
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* All rights reserved. |
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* |
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* This code is derived from software contributed to The NetBSD Foundation |
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* by UCHIYAMA Yasushi. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the NetBSD |
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* Foundation, Inc. and its contributors. |
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* 4. Neither the name of The NetBSD Foundation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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|
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/* |
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* 16bit timer 0:3 |
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* source: BUSCLK, H-BLNK |
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*/ |
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|
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#define EE_TIMER_MIN 0 |
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#define EE_TIMER_MAX 3 |
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#define LEGAL_TIMER(x) \ |
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(((x) >= EE_TIMER_MIN) && ((x) <= EE_TIMER_MAX)) |
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|
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/* Register address. all registers are 32bit wide */ |
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#define TIMER_REGBASE 0x10000000 |
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#define TIMER_REGSIZE 0x2000 |
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#define TIMER_OFS 0x800 |
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|
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#define T_COUNT_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + TIMER_OFS * (x))) |
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#define T_MODE_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \ |
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TIMER_OFS * (x) + 0x10)) |
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#define T_COMP_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \ |
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TIMER_OFS * (x) + 0x20)) |
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/* |
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* timer0, timer1 have `hold register'. |
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* (save T_COUNT when SBUS interrupt occured) |
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*/ |
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#define T_HOLD_REG(x) (TIMER_REGBASE + TIMER_OFS * (x) + 0x30) |
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|
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#define T0_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000000) |
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#define T0_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000010) |
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#define T0_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000020) |
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#define T0_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000030) |
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#define T1_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000800) |
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#define T1_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000810) |
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#define T1_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000820) |
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#define T1_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000830) |
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#define T2_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001000) |
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#define T2_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001010) |
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#define T2_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001020) |
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#define T3_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10001800) |
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#define T3_MODE_REG MIPS_PHYS_TO_KSEG1(0x10001810) |
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#define T3_COMP_REG MIPS_PHYS_TO_KSEG1(0x10001820) |
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|
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/* |
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* Tn_MODE: mode, status register. |
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*/ |
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#define T_MODE_CLKS_MASK 0x3 |
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#define T_MODE_CLKS(x) ((x) & T_MODE_CLKS_MASK) |
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#define T_MODE_CLKS_CLR(x) ((x) & ~T_MODE_CLKS_MASK) |
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|
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#define T_MODE_CLKS_BUSCLK1 0 /* 150Mhz */ |
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#define T_MODE_CLKS_BUSCLK16 1 /* 150 / 16 */ |
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#define T_MODE_CLKS_BUSCLK256 2 /* 150 / 256 */ |
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#define T_MODE_CLKS_HBLNK 3 /* H-Blank */ |
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|
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/* Gate Function Enabled */ |
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#define T_MODE_GATE 0x00000004 |
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/* Gate Selection */ |
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#define T_MODE_GATS_VBLNK 0x00000008 |
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/* Gate Mode */ |
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#define T_MODE_GATM_MASK 0x3 |
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#define T_MODE_GATM_SHIFT 4 |
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#define T_MODE_GATM(x) (((x) >> T_MODE_GATM_SHIFT) & T_MODE_GATM_MASK) |
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#define T_MODE_GATM_CLR(x) \ |
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((x) & ~(T_MODE_GATM_MASK << T_MODE_GATM_SHIFT)) |
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#define T_MODE_GATM_SET(x, val) \ |
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((x) | (((val) << T_MODE_GATM_SHIFT) & \ |
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(T_MODE_GATM_MASK << T_MODE_GATM_SHIFT))) |
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#define T_MODE_GATM_LOW 0x0 |
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#define T_MODE_GATM_POSEDGE 0x1 |
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#define T_MODE_GATM_NEGEDGE 0x2 |
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#define T_MODE_GATM_EDGE 0x3 |
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|
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/* Zero Return */ |
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#define T_MODE_ZRET 0x00000040 |
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/* Count Up Enable */ |
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#define T_MODE_CUE 0x00000080 |
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/* Compare-Interrupt Enable */ |
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#define T_MODE_CMPE 0x00000100 |
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/* Overflow-Interrupt Enable */ |
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#define T_MODE_OVFE 0x00000200 |
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/* Equal Flag (write clear) */ |
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#define T_MODE_EQUF 0x00000400 |
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/* Overflow Flag (write clear) */ |
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#define T_MODE_OVFF 0x00000800 |
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|
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/* |
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* Tn_COUNT: counter register |
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*/ |
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#define T_COUNT_MASK 0x0000ffff |
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#define T_COUNT(x) ((x) & T_COUNT_MASK) |
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|
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/* |
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* Tn_COMP: compare register |
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*/ |
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#define T_COMP_MASK 0x0000ffff |
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#define T_COMP(x) ((x) & T_COMP_MASK) |
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|
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/* |
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* Tn_HOLD: hold register |
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*/ |
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#define T_HOLD_MASK 0x0000ffff |
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#define T_HOLD(x) ((x) & T_HOLD_MASK) |
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