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/* GXemul: $Id: dreamcast_pvr.h,v 1.6 2006/10/31 08:27:26 debug Exp $ */ |
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/* $NetBSD: pvr.c,v 1.22 2006/04/12 19:38:22 jmmv Exp $ */ |
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|
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#ifndef DREAMCAST_PVR_H |
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#define DREAMCAST_PVR_H |
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|
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/* |
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* Note: This was pvr.c in NetBSD. It has been extended with reasonably |
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* similar symbolnames from http://www.ludd.luth.se/~jlo/dc/powervr-reg.txt. |
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* |
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* There are still many things missing. |
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*/ |
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|
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/*- |
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* Copyright (c) 2001 Marcus Comstedt. |
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* Copyright (c) 2001 Jason R. Thorpe. |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by Marcus Comstedt. |
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* 4. Neither the name of The NetBSD Foundation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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|
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/* |
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* Copyright (c) 1998, 1999 Tohru Nishimura. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by Tohru Nishimura |
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* for the NetBSD Project. |
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* 4. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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|
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#define PVRREG_FBSTART 0x05000000 |
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#define PVRREG_REGSTART 0x005f8000 |
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|
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#define PVRREG_REGSIZE 0x00002000 |
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|
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|
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#define PVRREG_ID 0x00 |
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|
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#define PVRREG_REVISION 0x04 |
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#define PVR_REVISION_MINOR_MASK 0xf |
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#define PVR_REVISION_MAJOR_MASK 0xf0 |
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#define PVR_REVISION_MAJOR_SHIFT 4 |
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|
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#define PVRREG_RESET 0x08 |
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#define PVR_RESET_TA 0x00000001 |
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#define PVR_RESET_PVR 0x00000002 |
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#define PVR_RESET_BUS 0x00000004 |
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|
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#define PVRREG_STARTRENDER 0x14 |
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|
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#define PVRREG_OB_ADDR 0x20 |
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/* Object Buffer start address. Bits 0..19 should always be zero. */ |
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#define PVR_OB_ADDR_MASK 0x00f00000 |
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|
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#define PVRREG_TILEBUF_ADDR 0x2c |
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#define PVR_TILEBUF_ADDR_MASK 0x00fffff8 |
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|
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#define PVRREG_SPANSORT 0x30 |
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#define PVR_SPANSORT_SPAN0 0x00000001 |
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#define PVR_SPANSORT_SPAN1 0x00000100 |
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#define PVR_SPANSORT_TSP_CACHE_ENABLE 0x00010000 |
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|
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#define PVRREG_BRDCOLR 0x40 |
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#define BRDCOLR_BLUE(x) ((x) << 0) |
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#define BRDCOLR_GREEN(x) ((x) << 8) |
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#define BRDCOLR_RED(x) ((x) << 16) |
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|
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#define PVRREG_DIWMODE 0x44 |
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#define DIWMODE_DE (1U << 0) /* display enable */ |
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#define DIWMODE_SD (1U << 1) /* scan double enable */ |
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#define DIWMODE_COL(x) ((x) << 2) |
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#define DIWMODE_COL_RGB555 DIWMODE_COL(0) /* RGB555, 16-bit */ |
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#define DIWMODE_COL_RGB565 DIWMODE_COL(1) /* RGB565, 16-bit */ |
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#define DIWMODE_COL_RGB888 DIWMODE_COL(2) /* RGB888, 24-bit */ |
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#define DIWMODE_COL_ARGB888 DIWMODE_COL(3) /* RGB888, 32-bit */ |
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#define DIWMODE_C (1U << 23) /* 2x clock enable (VGA) */ |
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#define DIWMODE_DE_MASK 0x00000001 |
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#define DIWMODE_SD_MASK 0x00000002 /* Line double */ |
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#define DIWMODE_COL_MASK 0x0000000c /* Pixel mode */ |
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#define DIWMODE_COL_SHIFT 2 |
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#define DIWMODE_EX_MASK 0x00000070 /* Extend bits */ |
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#define DIWMODE_EX_SHIFT 4 |
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#define DIWMODE_TH_MASK 0x0000ff00 /* ARGB8888 threshold */ |
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#define DIWMODE_TH_SHIFT 8 |
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#define DIWMODE_SL_MASK 0x003f0000 /* Strip Length */ |
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#define DIWMODE_SL_SHIFT 16 |
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#define DIWMODE_SE_MASK 0x00400000 /* Strip Buffer enabled */ |
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#define DIWMODE_C_MASK 0x00800000 /* Clock double */ |
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|
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#define PVRREG_FB_RENDER_CFG 0x48 |
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/* TODO */ |
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|
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#define PVRREG_FB_RENDER_MODULO 0x4c |
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#define FB_RENDER_MODULO_MASK 0x000001ff |
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/* TODO */ |
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|
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#define PVRREG_DIWADDRL 0x50 |
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|
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#define PVRREG_DIWADDRS 0x54 |
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|
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#define PVRREG_DIWSIZE 0x5c |
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#define DIWSIZE_DPL(x) ((x) << 0) /* pixel data per line */ |
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#define DIWSIZE_LPF(x) ((x) << 10) /* lines per field */ |
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#define DIWSIZE_MODULO(x) ((x) << 20) /* words to skip + 1 */ |
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#define DIWSIZE_MASK 0x3ff /* All fields are 10 bits. */ |
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#define DIWSIZE_DPL_SHIFT 0 |
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#define DIWSIZE_LPF_SHIFT 10 |
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#define DIWSIZE_MODULO_SHIFT 20 |
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|
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#define PVRREG_FB_RENDER_ADDR1 0x60 /* Odd interlace lines */ |
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|
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#define PVRREG_FB_RENDER_ADDR2 0x64 /* Even interlace lines */ |
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|
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#define PVRREG_VRAM_CFG1 0xa0 |
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#define VRAM_CFG1_GOOD_REFRESH_VALUE 0x20 |
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|
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#define PVRREG_VRAM_CFG2 0xa4 |
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#define VRAM_CFG2_UNKNOWN_MAGIC 0x0000001f |
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|
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#define PVRREG_VRAM_CFG3 0xa8 |
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#define VRAM_CFG3_UNKNOWN_MAGIC 0x15d1c951 |
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|
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#define PVRREG_FOG_TABLE_COL 0xb0 |
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|
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#define PVRREG_FOG_VERTEX_COL 0xb4 |
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|
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#define PVRREG_RASEVTPOS 0xcc |
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#define RASEVTPOS_POS2_MASK 0x000003ff |
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#define RASEVTPOS_POS1_MASK 0x03ff0000 |
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#define RASEVTPOS_POS1_SHIFT 16 |
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#define RASEVTPOS_BOTTOM(x) ((x) << 0) |
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#define RASEVTPOS_TOP(x) ((x) << 16) |
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|
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#define PVRREG_SYNCCONF 0xd0 |
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#define SYNCCONF_VP (1U << 0) /* V-sync polarity */ |
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#define SYNCCONF_HP (1U << 1) /* H-sync polarity */ |
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#define SYNCCONF_I (1U << 4) /* interlace */ |
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#define SYNCCONF_BC(x) (1U << 6) /* broadcast standard */ |
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#define SYNCCONF_VO (1U << 8) /* video output enable */ |
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#define SYNCCONF_VO_MASK 0x00000100 |
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#define SYNCCONF_BC_MASK 0x000000c0 |
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#define SYNCCONF_BC_SHIFT 6 |
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#define SYNCCONF_BC_VGA 0 |
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#define SYNCCONF_BC_NTSC 1 |
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#define SYNCCONF_BC_PAL 2 |
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#define SYNCCONF_I_MASK 0x00000010 |
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#define SYNCCONF_HP_MASK 0x00000004 /* Positive H-sync */ |
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#define SYNCCONF_VP_MASK 0x00000002 /* Positive V-sync */ |
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|
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#define PVRREG_BRDHORZ 0xd4 |
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#define BRDHORZ_STOP_MASK 0x0000ffff |
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#define BRDHORZ_START_MASK 0xffff0000 |
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#define BRDHORZ_START_SHIFT 16 |
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#define BRDHORZ_STOP(x) ((x) << 0) |
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#define BRDHORZ_START(x) ((x) << 16) |
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|
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#define PVRREG_SYNCSIZE 0xd8 |
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#define SYNCSIZE_H_MASK 0x0000ffff |
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#define SYNCSIZE_V_MASK 0xffff0000 |
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#define SYNCSIZE_V_SHIFT 16 |
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#define SYNCSIZE_H(x) ((x) << 0) |
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#define SYNCSIZE_V(x) ((x) << 16) |
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|
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#define PVRREG_BRDVERT 0xdc |
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#define BRDVERT_STOP_MASK 0x0000ffff |
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#define BRDVERT_START_MASK 0xffff0000 |
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#define BRDVERT_START_SHIFT 16 |
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#define BRDVERT_STOP(x) ((x) << 0) |
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#define BRDVERT_START(x) ((x) << 16) |
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|
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#define PVRREG_DIWCONF 0xe8 |
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#define DIWCONF_BLANK (1U << 3) /* blank screen */ |
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#define DIWCONF_LR (1U << 8) /* low-res (320 horizontal) */ |
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#define DIWCONF_MAGIC_MASK 0x003f0000 |
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#define DIWCONF_MAGIC (22 << 16) |
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|
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#define PVRREG_DIWHSTRT 0xec |
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#define DIWVSTRT_HPOS_MASK 0x000003ff |
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|
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#define PVRREG_DIWVSTRT 0xf0 |
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#define DIWVSTRT_V1_MASK 0x000003ff |
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#define DIWVSTRT_V2_MASK 0x03ff0000 |
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#define DIWVSTRT_V2_SHIFT 16 |
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#define DIWVSTRT_V1(x) ((x) << 0) |
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#define DIWVSTRT_V2(x) ((x) << 16) |
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|
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#define PVRREG_PALETTE_CFG 0x108 |
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#define PVR_PALETTE_CFG_MODE_MASK 0x3 |
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#define PVR_PALETTE_CFG_MODE_ARGB1555 0x0 |
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#define PVR_PALETTE_CFG_MODE_RGB565 0x1 |
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#define PVR_PALETTE_CFG_MODE_ARGB4444 0x2 |
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#define PVR_PALETTE_CFG_MODE_ARGB8888 0x3 |
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|
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#define PVRREG_SYNC_STAT 0x10c |
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#define PVR_SYNC_STAT_VPOS_MASK 0x000003ff |
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#define PVR_SYNC_STAT_INTERLACE_FIELD_EVEN 0x00000400 |
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#define PVR_SYNC_STAT_HBLANK 0x00001000 |
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#define PVR_SYNC_STAT_VBLANK 0x00002000 |
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|
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#define PVRREG_TA_OPB_START 0x124 |
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#define TA_OPB_START_MASK 0x00ffff80 |
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|
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#define PVRREG_TA_OB_START 0x128 |
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#define TA_OB_START_MASK 0x00fffff8 |
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|
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#define PVRREG_TA_OPB_END 0x12c |
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#define TA_OPB_END_MASK 0x00ffff80 |
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|
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#define PVRREG_TA_OB_END 0x130 |
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#define TA_OB_END_MASK 0x00fffff8 |
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|
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#define PVRREG_TA_OPB_POS 0x134 |
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#define TA_OPB_POS_MASK 0x00ffff80 |
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|
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#define PVRREG_TA_OB_POS 0x138 |
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#define TA_OB_POS_MASK 0x00fffff8 |
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|
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#define PVRREG_TILEBUF_SIZE 0x13c |
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#define TILEBUF_SIZE_HEIGHT_MASK 0xffff0000 |
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#define TILEBUF_SIZE_HEIGHT_SHIFT 16 |
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#define TILEBUF_SIZE_WIDTH_MASK 0x0000ffff |
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|
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#define PVRREG_TA_OPB_CFG 0x140 |
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#define TA_OPB_CFG_OPAQUEPOLY_MASK 0x00000003 |
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#define TA_OPB_CFG_OPAQUEMOD_MASK 0x00000030 |
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#define TA_OPB_CFG_OPAQUEMOD_SHIFT 4 |
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#define TA_OPB_CFG_TRANSPOLY_MASK 0x00000300 |
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#define TA_OPB_CFG_TRANSPOLY_SHIFT 8 |
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#define TA_OPB_CFG_TRANSMOD_MASK 0x00003000 |
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#define TA_OPB_CFG_TRANSMOD_SHIFT 12 |
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#define TA_OPB_CFG_PUNCHTHROUGH_MASK 0x00030000 |
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#define TA_OPB_CFG_PUNCHTHROUGH_SHIFT 16 |
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#define TA_OPB_CFG_OPBDIR 0x00100000 |
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|
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#define PVRREG_TA_INIT 0x144 |
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#define PVR_TA_INIT 0x80000000 |
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|
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#define PVRREG_YUV_ADDR 0x148 |
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#define PVR_YUV_ADDR_MASK 0x00ffffe0 |
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|
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#define PVRREG_YUV_CFG1 0x14c |
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/* TODO */ |
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|
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#define PVRREG_YUV_STAT 0x150 |
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/* Nr of currently converted 16x16 macro blocks. */ |
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#define PVR_YUV_STAT_BLOCKS_MASK 0x1fff |
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|
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#define PVRREG_TA_OPL_REINIT 0x160 |
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#define PVR_TA_OPL_REINIT 0x80000000 |
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|
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#define PVRREG_TA_OPL_INIT 0x164 |
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/* Start of Object Pointer List allocation in VRAM. */ |
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#define PVR_TA_OPL_INIT_MASK 0x00ffff80 |
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|
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#define PVRREG_FOG_TABLE 0x0200 |
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#define PVR_FOG_TABLE_SIZE 0x0200 |
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|
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#define PVRREG_PALETTE 0x1000 |
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#define PVR_PALETTE_SIZE 0x1000 |
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|
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#endif /* DREAMCAST_PVR_H */ |
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