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/* gxemul: $Id: dec_kn03.h,v 1.3 2005/03/05 12:34:02 debug Exp $ */ |
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/* The IOASIC stuff below seems to be using 0x40000 per slot */ |
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|
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/* $NetBSD: kn03.h,v 1.10 2000/02/29 04:41:57 nisimura Exp $ */ |
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|
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/*- |
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* Copyright (c) 1992, 1993 |
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* The Regents of the University of California. All rights reserved. |
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* |
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* This code is derived from software contributed to Berkeley by |
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* The Mach Operating System project at Carnegie-Mellon University, |
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* Ralph Campbell and Rick Macklem. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the University of |
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* California, Berkeley and its contributors. |
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* 4. Neither the name of the University nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* @(#)kn03.h 8.1 (Berkeley) 6/10/93 |
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*/ |
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|
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/* |
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* Mach Operating System |
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University |
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* All Rights Reserved. |
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* |
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* Permission to use, copy, modify and distribute this software and |
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* its documentation is hereby granted, provided that both the copyright |
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* notice and this permission notice appear in all copies of the |
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* software, derivative works or modified versions, and any portions |
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* thereof, and that both notices appear in supporting documentation. |
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* |
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" |
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND |
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. |
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* |
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* Carnegie Mellon requests users of this software to return to |
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* |
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU |
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* School of Computer Science |
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* Carnegie Mellon University |
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* Pittsburgh PA 15213-3890 |
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* |
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* any improvements or extensions that they make and grant Carnegie the |
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* rights to redistribute these changes. |
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*/ |
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/* |
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* Definitions specific to the KN03GA processors and 3MAX+ |
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* DECstation 5000/240 mother board. |
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*/ |
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|
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#ifndef MIPS_KN03_H |
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#define MIPS_KN03_H 1 |
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|
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/* |
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* 3MAX+'s Physical address space |
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*/ |
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#define KN03_PHYS_MIN 0x00000000 /* 512 Meg */ |
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#define KN03_PHYS_MAX 0x1fffffff |
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|
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/* |
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* Memory map |
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*/ |
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#define KN03_PHYS_MEMORY_START 0x00000000 |
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#define KN03_PHYS_MEMORY_END 0x1dffffff /* 480 Meg */ |
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|
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/* |
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* I/O map |
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*/ |
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#define KN03_PHYS_TC_0_START 0x1e000000 /* TURBOchannel, slot 0 */ |
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#define KN03_PHYS_TC_0_END 0x1e7fffff /* 8 Meg, option0 */ |
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|
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#define KN03_PHYS_TC_1_START 0x1e800000 /* TURBOchannel, slot 1 */ |
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#define KN03_PHYS_TC_1_END 0x1effffff /* 8 Meg, option1 */ |
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|
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#define KN03_PHYS_TC_2_START 0x1f000000 /* TURBOchannel, slot 2 */ |
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#define KN03_PHYS_TC_2_END 0x1f7fffff /* 8 Meg, option2 */ |
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|
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#define KN03_PHYS_TC_3_START 0x1f800000 /* TURBOchannel, slot 3 */ |
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#define KN03_PHYS_TC_3_END 0x1fffffff /* 8 Meg, system devices */ |
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|
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#define KN03_PHYS_TC_START KN03_PHYS_TC_0_START |
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#define KN03_PHYS_TC_END KN03_PHYS_TC_3_END |
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|
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#define KN03_TC_NSLOTS 4 |
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#define KN03_TC_MIN 0 |
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#define KN03_TC_MAX 2 /* don't look at system slot */ |
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|
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/* |
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* System module space (IOASIC) |
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*/ |
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#define KN03_SYS_ASIC ( KN03_PHYS_TC_3_START + 0x0000000 ) |
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#define KN03_SYS_ROM_START ( KN03_SYS_ASIC + IOASIC_SLOT_0_START ) |
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#define KN03_SYS_ASIC_REGS ( KN03_SYS_ASIC + IOASIC_SLOT_1_START ) |
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#define KN03_SYS_ETHER_ADDRESS ( KN03_SYS_ASIC + IOASIC_SLOT_2_START ) |
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#define KN03_SYS_LANCE ( KN03_SYS_ASIC + IOASIC_SLOT_3_START ) |
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#define KN03_SYS_SCC_0 ( KN03_SYS_ASIC + IOASIC_SLOT_4_START ) |
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#define KN03_SYS_SCC_1 ( KN03_SYS_ASIC + IOASIC_SLOT_6_START ) |
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#define KN03_SYS_CLOCK ( KN03_SYS_ASIC + IOASIC_SLOT_8_START ) |
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#define KN03_SYS_ERRADR ( KN03_SYS_ASIC + IOASIC_SLOT_9_START ) |
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#define KN03_SYS_ERRSYN ( KN03_SYS_ASIC + IOASIC_SLOT_10_START ) |
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#define KN03_SYS_CSR ( KN03_SYS_ASIC + IOASIC_SLOT_11_START ) |
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#define KN03_SYS_SCSI ( KN03_SYS_ASIC + IOASIC_SLOT_12_START ) |
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#define KN03_SYS_SCSI_DMA ( KN03_SYS_ASIC + IOASIC_SLOT_14_START ) |
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#define KN03_SYS_BOOT_ROM_START ( KN03_PHYS_TC_3_START + 0x400000 ) |
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#define KN03_SYS_BOOT_ROM_END ( KN03_PHYS_TC_3_START + 0x43ffff ) |
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|
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/* |
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* Interrupts |
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*/ |
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#define KN03_INT_FPA IP_LEV7 /* Floating Point coproc */ |
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#define KN03_INT_HALTB IP_LEV6 /* Halt button */ |
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#define KN03_INT_MEM IP_LEV5 /* Memory Errors */ |
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#define KN03_INT_RTC IP_LEV3 /* RTC clock */ |
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#define KN03_INT_ASIC IP_LEV2 /* All turbochannel */ |
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|
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#define KN03_REG_SCSI_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCSI_DMAPTR ) |
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#define KN03_REG_SCSI_DMANPTR ( KN03_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) |
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#define KN03_REG_LANCE_DMAPTR ( KN03_SYS_ASIC + IOASIC_LANCE_DMAPTR ) |
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#define KN03_REG_SCC_T1_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) |
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#define KN03_REG_SCC_R1_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) |
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#define KN03_REG_SCC_T2_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) |
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#define KN03_REG_SCC_R2_DMAPTR ( KN03_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) |
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#define KN03_REG_CSR ( KN03_SYS_ASIC + IOASIC_CSR ) |
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#define KN03_REG_INTR ( KN03_SYS_ASIC + IOASIC_INTR ) |
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#define KN03_REG_IMSK ( KN03_SYS_ASIC + IOASIC_IMSK ) |
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#define KN03_REG_CURADDR ( KN03_SYS_ASIC + IOASIC_CURADDR ) |
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|
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#define KN03_REG_LANCE_DECODE ( KN03_SYS_ASIC + IOASIC_LANCE_DECODE ) |
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#define KN03_REG_SCSI_DECODE ( KN03_SYS_ASIC + IOASIC_SCSI_DECODE ) |
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#define KN03_REG_SCC0_DECODE ( KN03_SYS_ASIC + IOASIC_SCC0_DECODE ) |
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#define KN03_REG_SCC1_DECODE ( KN03_SYS_ASIC + IOASIC_SCC1_DECODE ) |
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# define KN03_LANCE_CONFIG 3 |
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# define KN03_SCSI_CONFIG 14 |
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# define KN03_SCC0_CONFIG (0x10|4) |
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# define KN03_SCC1_CONFIG (0x10|6) |
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|
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#define KN03_REG_SCSI_SCR ( KN03_SYS_ASIC + IOASIC_SCSI_SCR ) |
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#define KN03_REG_SCSI_SDR0 ( KN03_SYS_ASIC + IOASIC_SCSI_SDR0 ) |
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#define KN03_REG_SCSI_SDR1 ( KN03_SYS_ASIC + IOASIC_SCSI_SDR1 ) |
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|
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/* NOTES |
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|
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Memory access priority is, from higher to lower: |
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- DRAM refresh |
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- IO DMA (IO Control ASIC) |
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- Slot 2 DMA |
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- Slot 1 DMA |
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- Slot 0 DMA |
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- Processor |
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|
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*/ |
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|
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/* |
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* More system registers defines (IO Control ASIC) |
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*/ |
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/* (re)defines for the system Status and Control register (SSR) */ |
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/* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ |
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#define KN03_CSR_LEDS 0x000000ff /* rw */ |
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#define KN03_CSR_BNK32M 0x00000400 /* rw Memory bank stride */ |
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#define KN03_CSR_CORRECT 0x00002000 /* rw ECC corrects single bit */ |
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#define KN03_CSR_ECCMD 0x0000c000 /* rw ECC logic mode */ |
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|
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/* (re)defines for the System Interrupt and Mask Registers */ |
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/* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ |
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#define KN03_INTR_PBNO 0x00000001 /* ro */ |
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#define KN03_INTR_PBNC 0x00000002 /* ro */ |
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#define KN03_INTR_SCSI_FIFO 0x00000004 /* ro */ |
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#define KN03_INTR_PSWARN 0x00000010 /* ro */ |
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#define KN03_INTR_CLOCK 0x00000020 /* ro */ |
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#define KN03_INTR_SCC_0 0x00000040 /* ro */ |
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#define KN03_INTR_SCC_1 0x00000080 /* ro */ |
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#define KN03_INTR_LANCE 0x00000100 /* ro */ |
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#define KN03_INTR_SCSI 0x00000200 /* ro */ |
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#define KN03_INTR_NRMOD_JUMPER 0x00000400 /* ro */ |
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#define KN03_INTR_TC_0 0x00000800 /* ro */ |
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#define KN03_INTR_TC_1 0x00001000 /* ro */ |
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#define KN03_INTR_TC_2 0x00002000 /* ro */ |
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#define KN03_INTR_NVR_JUMPER 0x00004000 /* ro */ |
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#define KN03_INTR_PROD_JUMPER 0x00008000 /* ro */ |
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|
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#define KN03_INTR_ASIC 0xff0f0004 |
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#define KN03_IM0 0xff0f3bf0 /* all good ones enabled */ |
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|
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/* |
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* Error Address Register Bit Definitions |
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*/ |
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#define KN03_ERR_ADDRESS 0x07ffffff /* phys address */ |
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#define KN03_ERR_RESERVED 0x08000000 /* unused */ |
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#define KN03_ERR_ECCERR 0x10000000 /* ECC error */ |
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#define KN03_ERR_WRITE 0x20000000 /* read/write transaction */ |
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#define KN03_ERR_CPU 0x40000000 /* CPU or device initiator */ |
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#define KN03_ERR_VALID 0x80000000 /* Info is valid */ |
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|
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/* ECC check/syndrome status register */ |
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#define KN03_ECC_SYNLO 0x0000007f /* syndrome, even bank */ |
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#define KN03_ECC_SNGLO 0x00000080 /* single bit err, " */ |
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#define KN03_ECC_CHKLO 0x00007f00 /* check bits, " " */ |
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#define KN03_ECC_VLDLO 0x00008000 /* info valid for " */ |
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#define KN03_ECC_SYNHI 0x007f0000 /* syndrome, odd bank */ |
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#define KN03_ECC_SNGHI 0x00800000 /* single bit err, " */ |
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#define KN03_ECC_CHKHI 0x7f000000 /* check bits, " " */ |
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#define KN03_ECC_VLDHI 0x80000000 /* info valid for " */ |
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|
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#endif /* MIPS_KN03_H */ |
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