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/* GXemul: $Id: dc21285reg.h,v 1.1 2005/09/13 20:56:54 debug Exp $ */ |
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/* $NetBSD: dc21285reg.h,v 1.4 2003/01/17 22:29:43 thorpej Exp $ */ |
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|
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#ifndef DC21285REG_H |
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#define DC21285REG_H |
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|
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/* |
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* Copyright (c) 1997,1998 Mark Brinicombe. |
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* Copyright (c) 1997,1998 Causality Limited |
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* All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by Mark Brinicombe |
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* for the NetBSD Project. |
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* 4. The name of the company nor the name of the author may be used to |
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* endorse or promote products derived from this software without specific |
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* prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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*/ |
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|
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/* |
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* DC21285 register definitions |
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*/ |
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|
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/* PCI registers in CSR space */ |
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|
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#define VENDOR_ID 0x00 |
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#define DC21285_VENDOR_ID 0x1011 |
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#define DEVICE_ID 0x02 |
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#define DC21285_DEVICE_ID 0x1065 |
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#define REVISION 0x08 |
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#define CLASS 0x0A |
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|
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/* Other PCI control / status registers */ |
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|
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#define OUTBOUND_INT_STATUS 0x030 |
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#define OUTBOUND_INT_MASK 0x034 |
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#define I2O_INBOUND_FIFO 0x040 |
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#define I2O_OUTBOUND_FIFO 0x044 |
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|
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/* Mailbox registers */ |
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|
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#define MAILBOX_0 0x050 |
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#define MAILBOX_1 0x054 |
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#define MAILBOX_2 0x058 |
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#define MAILBOX_3 0x05C |
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|
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#define DOORBELL 0x060 |
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#define DOORBELL_SETUP 0x064 |
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#define ROM_WRITE_BYTE_ADDRESS 0x068 |
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|
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/* DMA Channel registers */ |
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|
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#define DMA_CHAN_1_BYTE_COUNT 0x80 |
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#define DMA_CHAN_1_PCI_ADDR 0x84 |
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#define DMA_CHAN_1_SDRAM_ADDR 0x88 |
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#define DMA_CHAN_1_DESCRIPT 0x8C |
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#define DMA_CHAN_1_CONTROL 0x90 |
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#define DMA_CHAN_2_BYTE_COUNT 0xA0 |
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#define DMA_CHAN_2_PCI_ADDR 0xA4 |
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#define DMA_CHAN_2_SDRAM_ADDR 0xA8 |
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#define DMA_CHAN_2_DESCRIPTOR 0xAC |
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#define DMA_CHAN_2_CONTROL 0xB0 |
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|
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/* Offsets into DMA descriptor */ |
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|
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#define DMA_BYTE_COUNT 0 |
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#define DMA_PCI_ADDRESS 4 |
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#define DMA_SDRAM_ADDRESS 8 |
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#define DMA_NEXT_DESCRIPTOR 12 |
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|
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/* DMA byte count register bits */ |
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|
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#define DMA_INTERBURST_SHIFT 24 |
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#define DMA_PCI_TO_SDRAM 0 |
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#define DMA_SDRAM_TO_PCI (1 << 30) |
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#define DMA_END_CHAIN (1 << 31) |
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|
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/* DMA control bits */ |
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|
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#define DMA_ENABLE (1 << 0) |
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#define DMA_TRANSFER_DONE (1 << 2) |
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#define DMA_ERROR (1 << 3) |
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#define DMA_REGISTOR_DESCRIPTOR (1 << 4) |
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#define DMA_PCI_MEM_READ (0 << 5) |
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#define DMA_PCI_MEM_READ_LINE (1 << 5) |
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#define DMA_PCI_MEM_READ_MULTI1 (2 << 5) |
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#define DMA_PCI_MEM_READ_MULTI2 (3 << 5) |
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#define DMA_CHAIN_DONE (1 << 7) |
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#define DMA_INTERBURST_4 (0 << 8) |
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#define DMA_INTERBURST_8 (1 << 8) |
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#define DMA_INTERBURST_16 (2 << 8) |
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#define DMA_INTERBURST_32 (3 << 8) |
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#define DMA_PCI_LENGTH_8 0 |
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#define DMA_PCI_LENGTH_16 (1 << 15) |
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#define DMA_SDRAM_LENGTH_1 (0 << 16) |
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#define DMA_SDRAM_LENGTH_2 (1 << 16) |
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#define DMA_SDRAM_LENGTH_4 (2 << 16) |
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#define DMA_SDRAM_LENGTH_8 (3 << 16) |
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#define DMA_SDRAM_LENGTH_16 (4 << 16) |
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|
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/* CSR Base Address Mask */ |
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|
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#define CSR_BA_MASK 0x0F8 |
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#define CSR_MASK_128B 0x00000000 |
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#define CSR_MASK_512KB 0x00040000 |
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#define CSR_MASK_1MB 0x000C0000 |
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#define CSR_MASK_2MB 0x001C0000 |
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#define CSR_MASK_4MB 0x003C0000 |
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#define CSR_MASK_8MB 0x007C0000 |
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#define CSR_MASK_16MB 0x00FC0000 |
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#define CSR_MASK_32MB 0x01FC0000 |
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#define CSR_MASK_64MB 0x03FC0000 |
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#define CSR_MASK_128MB 0x07FC0000 |
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#define CSR_MASK_256MB 0x0FFC0000 |
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#define CSR_BA_OFFSET 0x0FC |
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|
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/* SDRAM Base Address Mask */ |
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|
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#define SDRAM_BA_MASK 0x100 |
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#define SDRAM_MASK_256KB 0x00000000 |
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#define SDRAM_MASK_512KB 0x00040000 |
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#define SDRAM_MASK_1MB 0x000C0000 |
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#define SDRAM_MASK_2MB 0x001C0000 |
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#define SDRAM_MASK_4MB 0x003C0000 |
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#define SDRAM_MASK_8MB 0x007C0000 |
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#define SDRAM_MASK_16MB 0x00FC0000 |
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#define SDRAM_MASK_32MB 0x01FC0000 |
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#define SDRAM_MASK_64MB 0x03FC0000 |
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#define SDRAM_MASK_128MB 0x07FC0000 |
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#define SDRAM_MASK_256MB 0x0FFC0000 |
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#define SDRAM_WINDOW_DISABLE (1 << 31) |
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#define SDRAM_BA_OFFSET 0x104 |
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|
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/* Expansion ROM Base Address Mask */ |
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|
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#define EXPANSION_ROM_BA_MASK 0x108 |
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#define ROM_MASK_1MB 0x00000000 |
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#define ROM_MASK_2MB 0x00100000 |
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#define ROM_MASK_4MB 0x00300000 |
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#define ROM_MASK_8MB 0x00700000 |
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#define ROM_MASK_16MB 0x00F00000 |
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#define ROM_WINDOW_DISABLE (1 << 31) |
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|
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/* SDRAM configuration */ |
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|
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#define SDRAM_TIMING 0x10C |
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#define SDRAM_ARRAY_SIZE_0 0x0 |
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#define SDRAM_ARRAY_SIZE_1MB 0x1 |
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#define SDRAM_ARRAY_SIZE_2MB 0x2 |
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#define SDRAM_ARRAY_SIZE_4MB 0x3 |
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#define SDRAM_ARRAY_SIZE_8MB 0x4 |
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#define SDRAM_ARRAY_SIZE_16MB 0x5 |
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#define SDRAM_ARRAY_SIZE_32MB 0x6 |
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#define SDRAM_ARRAY_SIZE_64MB 0x7 |
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#define SDRAM_2_BANKS 0 |
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#define SDRAM_4_BANKS (1 << 3) |
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#define SDRAM_ADDRESS_MUX_SHIFT 4 |
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#define SDRAM_ARRAY_BASE_SHIFT 20 |
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#define SDRAM_ADDRESS_SIZE_0 0x110 |
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#define SDRAM_ADDRESS_SIZE_1 0x114 |
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#define SDRAM_ADDRESS_SIZE_2 0x118 |
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#define SDRAM_ADDRESS_SIZE_3 0x11C |
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|
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/* I2O registers */ |
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|
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#define I2O_INBOUND_FREE_HEAD 0x120 |
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#define I2O_INBOUND_POST_TAIL 0x124 |
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#define I2O_OUTBOUND_POST_HEAD 0x128 |
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#define I2O_OUTBOUND_FREE_TAIL 0x12c |
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#define I2O_INBOUND_FREE_COUNT 0x130 |
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#define I2O_OUTBOUND_POST_COUNT 0x134 |
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#define I2O_INBOUND_POST_COUNT 0x138 |
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|
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/* Control register */ |
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|
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#define SA_CONTROL 0x13C |
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#define INITIALIZE_COMPLETE (1 << 0) |
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#define ASSERT_SERR (1 << 1) |
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#define RECEIVED_SERR (1 << 3) |
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#define SA_SDRAM_PARITY_ERROR (1 << 4) |
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#define PCI_SDRAM_PARITY_ERROR (1 << 5) |
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#define DMA_SDRAM_PARITY_ERROR (1 << 6) |
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#define DISCARD_TIMER_EXPIRED (1 << 8) |
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#define PCI_NOT_RESET (1 << 9) |
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#define WATCHDOG_ENABLE (1 << 13) |
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#define I2O_SIZE_256 (0 << 10) |
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#define I2O_SIZE_512 (1 << 10) |
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#define I2O_SIZE_1024 (2 << 10) |
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#define I2O_SIZE_2048 (3 << 10) |
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#define I2O_SIZE_4096 (4 << 10) |
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#define I2O_SIZE_8192 (5 << 10) |
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#define I2O_SIZE_16384 (6 << 10) |
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#define I2O_SIZE_32768 (7 << 10) |
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#define ROM_WIDTH_8 (3 << 14) |
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#define ROM_WIDTH_16 (1 << 14) |
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#define ROM_WIDTH_32 (2 << 14) |
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#define ROM_ACCESS_TIME_SHIFT 16 |
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#define ROM_BURST_TIME_SHIFT 20 |
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#define ROM_TRISTATE_TIME_SHIFT 24 |
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#define XCS_DIRECTION_SHIFT 28 |
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#define PCI_CENTRAL_FUNCTION (1 << 31) |
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|
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#define PCI_ADDRESS_EXTENSION 0x140 |
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#define PREFETCHABLE_MEM_RANGE 0x144 |
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|
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/* XBUS / PCI Arbiter registers */ |
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|
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#define XBUS_CYCLE_ARBITER 0x148 |
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#define XBUS_CYCLE_0_SHIFT 0 |
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#define XBUS_CYCLE_1_SHIFT 3 |
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#define XBUS_CYCLE_2_SHIFT 6 |
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#define XBUS_CYCLE_3_SHIFT 9 |
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#define XBUS_CYCLE_STROBE_SHIFT 12 |
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#define XBUS_PCI_ARBITER (1 << 23) |
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#define XBUS_INT_IN_L0_LOW 0 |
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#define XBUS_INT_IN_L0_HIGH (1 << 24) |
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#define XBUS_INT_IN_L1_LOW 0 |
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#define XBUS_INT_IN_L1_HIGH (1 << 25) |
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#define XBUS_INT_IN_L2_LOW 0 |
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#define XBUS_INT_IN_L2_HIGH (1 << 26) |
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#define XBUS_INT_IN_L3_LOW 0 |
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#define XBUS_INT_IN_L3_HIGH (1 << 27) |
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#define XBUS_INT_XCS0_LOW 0 |
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#define XBUS_INT_XCS0_HIGH (1 << 28) |
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#define XBUS_INT_XCS1_LOW 0 |
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#define XBUS_INT_XCS1_HIGH (1 << 29) |
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#define XBUS_INT_XCS2_LOW 0 |
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#define XBUS_INT_XCS2_HIGH (1 << 30) |
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#define XBUS_PCI_INT_REQUEST (1 << 31) |
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|
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#define XBUS_IO_STROBE_MASK 0x14C |
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#define XBUS_IO_STROBE_0_SHIFT 0 |
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#define XBUS_IO_STROBE_2_SHIFT 8 |
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#define XBUS_IO_STROBE_3_SHIFT 16 |
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#define XBUS_IO_STROBE_4_SHIFT 24 |
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|
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#define DOORBELL_PCI_MASK 0x150 |
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#define DOORBELL_SA_MASK 0x154 |
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|
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/* UART registers */ |
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|
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#define UART_DATA 0x160 |
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#define UART_RX_STAT 0x164 |
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#define UART_PARITY_ERROR 0x01 |
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#define UART_FRAME_ERROR 0x02 |
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#define UART_OVERRUN_ERROR 0x04 |
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#define UART_RX_ERROR (UART_PARITY_ERROR | UART_FRAME_ERROR \ |
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| UART_OVERRUN_ERROR) |
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#define UART_H_UBRLCR 0x168 |
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#define UART_BREAK 0x01 |
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#define UART_PARITY_ENABLE 0x02 |
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#define UART_ODD_PARITY 0x00 |
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#define UART_EVEN_PARITY 0x04 |
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#define UART_STOP_BITS_1 0x00 |
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#define UART_STOP_BITS_2 0x08 |
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#define UART_ENABLE_FIFO 0x10 |
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#define UART_DATA_BITS_5 0x00 |
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#define UART_DATA_BITS_6 0x20 |
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#define UART_DATA_BITS_7 0x40 |
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#define UART_DATA_BITS_8 0x60 |
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#define UART_M_UBRLCR 0x16C |
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#define UART_L_UBRLCR 0x170 |
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#define UART_BRD(fclk, x) (((fclk) / 4 / 16 / x) - 1) |
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|
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#define UART_CONTROL 0x174 |
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#define UART_ENABLE 0x01 |
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#define UART_SIR_ENABLE 0x02 |
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#define UART_IRDA_ENABLE 0x04 |
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#define UART_FLAGS 0x178 |
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#define UART_TX_BUSY 0x08 |
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#define UART_RX_FULL 0x10 |
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#define UART_TX_EMPTY 0x20 |
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|
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/* Interrupt numbers for IRQ and FIQ registers */ |
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|
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#define IRQ_RESERVED0 0x00 |
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#define IRQ_SOFTINT 0x01 |
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#define IRQ_SERIAL_RX 0x02 |
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#define IRQ_SERIAL_TX 0x03 |
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#define IRQ_TIMER_1 0x04 |
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#define IRQ_TIMER_2 0x05 |
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#define IRQ_TIMER_3 0x06 |
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#define IRQ_TIMER_4 0x07 |
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#define IRQ_IN_L0 0x08 |
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#define IRQ_IN_L1 0x09 |
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#define IRQ_IN_L2 0x0A |
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#define IRQ_IN_L3 0x0B |
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#define IRQ_XCS_L0 0x0C |
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#define IRQ_XCS_L1 0x0D |
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#define IRQ_XCS_L2 0x0E |
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#define IRQ_DOORBELL 0x0F |
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#define IRQ_DMA_1 0x10 |
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#define IRQ_DMA_2 0x11 |
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#define IRQ_PCI 0x12 |
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#define IRQ_PMCSR 0x13 |
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#define IRQ_RESERVED1 0x14 |
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#define IRQ_RESERVED2 0x15 |
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#define IRQ_BIST 0x16 |
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#define IRQ_SERR 0x17 |
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#define IRQ_SDRAM_PARITY 0x18 |
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#define IRQ_I2O 0x19 |
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#define IRQ_RESERVED3 0x1A |
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#define IRQ_DISCARD_TIMER 0x1B |
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#define IRQ_DATA_PARITY 0x1C |
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#define IRQ_MASTER_ABORT 0x1D |
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#define IRQ_TARGET_ABORT 0x1E |
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#define IRQ_PARITY 0x1F |
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|
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/* IRQ and FIQ status / enable registers */ |
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|
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#define IRQ_STATUS 0x180 |
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#define IRQ_RAW_STATUS 0x184 |
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#define IRQ_ENABLE 0x188 |
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#define IRQ_ENABLE_SET 0x188 |
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#define IRQ_ENABLE_CLEAR 0x18c |
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#define IRQ_SOFT 0x190 |
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|
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#define FIQ_STATUS 0x280 |
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#define FIQ_RAW_STATUS 0x284 |
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#define FIQ_ENABLE 0x288 |
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#define FIQ_ENABLE_SET 0x288 |
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#define FIQ_ENABLE_CLEAR 0x28c |
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#define FIQ_SOFT 0x290 |
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|
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/* Timer registers */ |
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|
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/* Relative offsets and bases */ |
| 349 |
|
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#define TIMER_LOAD 0x00 |
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#define TIMER_VALUE 0x04 |
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#define TIMER_CONTROL 0x08 |
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#define TIMER_CLEAR 0x0C |
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#define TIMER_1_BASE 0x300 |
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#define TIMER_2_BASE 0x320 |
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#define TIMER_3_BASE 0x340 |
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#define TIMER_4_BASE 0x360 |
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|
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/* Control register bits */ |
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|
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#define TIMER_FCLK 0x00 |
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#define TIMER_FCLK_16 0x04 |
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#define TIMER_FCLK_256 0x08 |
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#define TIMER_EXTERNAL 0x0C |
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#define TIMER_MODE_FREERUN 0x00 |
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#define TIMER_MODE_PERIODIC 0x40 |
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#define TIMER_ENABLE 0x80 |
| 368 |
|
| 369 |
/* Maximum timer value */ |
| 370 |
|
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#define TIMER_MAX_VAL 0x00FFFFFF |
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|
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/* Specific registers */ |
| 374 |
|
| 375 |
#define TIMER_1_LOAD 0x300 |
| 376 |
#define TIMER_1_VALUE 0x304 |
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#define TIMER_1_CONTROL 0x308 |
| 378 |
#define TIMER_1_CLEAR 0x30C |
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#define TIMER_2_LOAD 0x320 |
| 380 |
#define TIMER_2_VALUE 0x324 |
| 381 |
#define TIMER_2_CONTROL 0x328 |
| 382 |
#define TIMER_2_CLEAR 0x32C |
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#define TIMER_3_LOAD 0x340 |
| 384 |
#define TIMER_3_VALUE 0x344 |
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#define TIMER_3_CONTROL 0x348 |
| 386 |
#define TIMER_3_CLEAR 0x34C |
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#define TIMER_4_LOAD 0x360 |
| 388 |
#define TIMER_4_VALUE 0x364 |
| 389 |
#define TIMER_4_CONTROL 0x368 |
| 390 |
#define TIMER_4_CLEAR 0x36C |
| 391 |
|
| 392 |
/* Miscellaneous definitions */ |
| 393 |
|
| 394 |
#ifndef FCLK |
| 395 |
#define FCLK 50000000 |
| 396 |
#endif |
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|
| 398 |
#endif /* DC21285REG_H */ |
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