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#ifndef CPU_PPC_H |
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#define CPU_PPC_H |
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|
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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_ppc.h,v 1.69 2007/02/16 19:57:56 debug Exp $ |
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*/ |
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|
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#include "misc.h" |
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|
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|
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struct cpu_family; |
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|
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#define MODE_PPC 0 |
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#define MODE_POWER 1 |
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|
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/* PPC CPU types: */ |
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struct ppc_cpu_type_def { |
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char *name; |
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int pvr; |
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int bits; |
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int flags; |
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int icache_shift; |
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int ilinesize; |
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int iway; |
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int dcache_shift; |
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int dlinesize; |
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int dway; |
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int l2cache_shift; |
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int l2linesize; |
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int l2way; |
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int altivec; |
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|
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/* TODO: POWER vs PowerPC? */ |
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}; |
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|
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/* Flags: */ |
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#define PPC_NOFP 1 |
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#define PPC_601 2 |
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#define PPC_603 4 |
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#define PPC_NO_DEC 8 /* No DEC (decrementer) SPR */ |
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|
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/* |
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* TODO: Most of these just bogus |
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*/ |
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|
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#define PPC_CPU_TYPE_DEFS { \ |
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{ "PPC405GP", 0x40110000, 32, PPC_NOFP|PPC_NO_DEC, \ |
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13,5,2, 13,5,2, 0,5,1, 0 }, \ |
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{ "PPC601", 0, 32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },\ |
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{ "PPC603", 0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\ |
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{ "PPC603e", 0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\ |
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{ "PPC604", 0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ |
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{ "PPC620", 0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 }, \ |
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{ "MPC7400", 0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \ |
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{ "PPC750", 0x00084202, 32, 0, 15,5,2, 15,5,2, 20,5,1, 0 }, \ |
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{ "G4e", 0, 32, 0, 15,5,8, 15,5,8, 18,5,8, 1 }, \ |
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{ "PPC970", 0x00390000, 64, 0, 16,7,1, 15,7,2, 19,7,1, 1 }, \ |
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{ NULL, 0, 0,0,0,0,0,0,0,0,0,0,0,0 } \ |
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} |
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|
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#define PPC_NGPRS 32 |
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#define PPC_NFPRS 32 |
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#define PPC_NVRS 32 |
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#define PPC_N_TGPRS 4 |
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|
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#define PPC_N_IC_ARGS 3 |
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#define PPC_INSTR_ALIGNMENT_SHIFT 2 |
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#define PPC_IC_ENTRIES_SHIFT 10 |
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#define PPC_IC_ENTRIES_PER_PAGE (1 << PPC_IC_ENTRIES_SHIFT) |
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#define PPC_PC_TO_IC_ENTRY(a) (((a)>>PPC_INSTR_ALIGNMENT_SHIFT) \ |
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& (PPC_IC_ENTRIES_PER_PAGE-1)) |
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#define PPC_ADDR_TO_PAGENR(a) ((a) >> (PPC_IC_ENTRIES_SHIFT \ |
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+ PPC_INSTR_ALIGNMENT_SHIFT)) |
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|
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#define PPC_L2N 17 |
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#define PPC_L3N 18 |
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|
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DYNTRANS_MISC_DECLARATIONS(ppc,PPC,uint64_t) |
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DYNTRANS_MISC64_DECLARATIONS(ppc,PPC,uint8_t) |
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|
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#define PPC_MAX_VPH_TLB_ENTRIES 128 |
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|
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|
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struct ppc_cpu { |
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struct ppc_cpu_type_def cpu_type; |
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|
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uint64_t of_emul_addr; |
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|
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int mode; /* MODE_PPC or MODE_POWER */ |
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int bits; /* 32 or 64 */ |
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|
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int irq_asserted; /* External Interrupt flag */ |
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int dec_intr_pending;/* Decrementer interrupt pending */ |
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uint64_t zero; /* A zero register */ |
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|
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uint32_t cr; /* Condition Register */ |
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uint32_t fpscr; /* FP Status and Control Register */ |
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uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */ |
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uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */ |
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|
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uint64_t vr_hi[PPC_NVRS];/* 128-bit Vector registers */ |
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uint64_t vr_lo[PPC_NVRS];/* (Hi and lo 64-bit parts) */ |
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|
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uint64_t msr; /* Machine state register */ |
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uint64_t tgpr[PPC_N_TGPRS];/*Temporary gpr 0..3 */ |
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|
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uint32_t sr[16]; /* Segment registers. */ |
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uint64_t spr[1024]; |
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|
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uint64_t ll_addr; /* Load-linked / store-conditional */ |
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int ll_bit; |
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|
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|
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/* |
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* Instruction translation cache and Virtual->Physical->Host |
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* address translation: |
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*/ |
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DYNTRANS_ITC(ppc) |
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VPH_TLBS(ppc,PPC) |
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VPH32(ppc,PPC,uint64_t,uint8_t) |
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VPH64(ppc,PPC,uint8_t) |
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}; |
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|
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|
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/* Machine status word bits: (according to Book 3) */ |
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#define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */ |
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/* bits 62..61 are reserved */ |
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#define PPC_MSR_HV (1ULL << 60) /* Hypervisor */ |
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/* bits 59..17 are reserved */ |
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#define PPC_MSR_VEC (1 << 25) /* Altivec Enable */ |
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#define PPC_MSR_TGPR (1 << 17) /* Temporary gpr0..3 */ |
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#define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */ |
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#define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */ |
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#define PPC_MSR_PR (1 << 14) /* Problem/Privilege State */ |
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#define PPC_MSR_FP (1 << 13) /* Floating-Point Available */ |
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#define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */ |
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#define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */ |
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#define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */ |
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#define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */ |
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#define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */ |
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#define PPC_MSR_IP (1 << 6) /* Vector Table at 0xfff00000 */ |
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#define PPC_MSR_IR (1 << 5) /* Instruction Relocate */ |
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#define PPC_MSR_DR (1 << 4) /* Data Relocate */ |
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#define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */ |
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#define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */ |
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#define PPC_MSR_LE (1) /* Little-Endian Mode */ |
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|
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/* Floating-point Status: */ |
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#define PPC_FPSCR_FX (1 << 31) /* Exception summary */ |
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#define PPC_FPSCR_FEX (1 << 30) /* Enabled Exception summary */ |
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#define PPC_FPSCR_VX (1 << 29) /* Invalid Operation summary */ |
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/* .. TODO */ |
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#define PPC_FPSCR_VXNAN (1 << 24) |
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/* .. TODO */ |
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#define PPC_FPSCR_FPCC 0x0000f000 |
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#define PPC_FPSCR_FPCC_SHIFT 12 |
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#define PPC_FPSCR_FL (1 << 15) /* Less than */ |
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#define PPC_FPSCR_FG (1 << 14) /* Greater than */ |
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#define PPC_FPSCR_FE (1 << 13) /* Equal or Zero */ |
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#define PPC_FPSCR_FU (1 << 12) /* Unordered or NaN */ |
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|
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/* Exceptions: */ |
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#define PPC_EXCEPTION_DSI 0x3 /* Data Storage Interrupt */ |
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#define PPC_EXCEPTION_ISI 0x4 /* Instruction Storage Interrupt */ |
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#define PPC_EXCEPTION_EI 0x5 /* External interrupt */ |
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#define PPC_EXCEPTION_FPU 0x8 /* Floating-Point unavailable */ |
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#define PPC_EXCEPTION_DEC 0x9 /* Decrementer */ |
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#define PPC_EXCEPTION_SC 0xc /* Syscall */ |
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|
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/* XER bits: */ |
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#define PPC_XER_SO (1UL << 31) /* Summary Overflow */ |
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#define PPC_XER_OV (1 << 30) /* Overflow */ |
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#define PPC_XER_CA (1 << 29) /* Carry */ |
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|
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|
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/* cpu_ppc.c: */ |
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int ppc_run_instr(struct cpu *cpu); |
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int ppc32_run_instr(struct cpu *cpu); |
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void ppc_exception(struct cpu *cpu, int exception_nr); |
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void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void ppc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void ppc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void ppc_init_64bit_dummy_tables(struct cpu *cpu); |
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int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int ppc_cpu_family_init(struct cpu_family *); |
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|
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/* memory_ppc.c: */ |
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int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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|
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#endif /* CPU_PPC_H */ |
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