/[gxemul]/upstream/0.4.4/src/include/cpu_ppc.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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trunk/src/include/cpu_ppc.h revision 20 by dpavlin, Mon Oct 8 16:19:23 2007 UTC upstream/0.4.4/src/include/cpu_ppc.h revision 35 by dpavlin, Mon Oct 8 16:21:26 2007 UTC
# Line 2  Line 2 
2  #define CPU_PPC_H  #define CPU_PPC_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_ppc.h,v 1.55 2005/11/24 01:15:07 debug Exp $   *  $Id: cpu_ppc.h,v 1.69 2007/02/16 19:57:56 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 63  struct ppc_cpu_type_def { Line 63  struct ppc_cpu_type_def {
63  #define PPC_NOFP                1  #define PPC_NOFP                1
64  #define PPC_601                 2  #define PPC_601                 2
65  #define PPC_603                 4  #define PPC_603                 4
66  /*  TODO: Most of these just bogus  */  #define PPC_NO_DEC              8       /*  No DEC (decrementer) SPR  */
67    
68    /*
69     *  TODO: Most of these just bogus
70     */
71    
72  #define PPC_CPU_TYPE_DEFS       {                                       \  #define PPC_CPU_TYPE_DEFS       {                                       \
73          { "PPC405GP",   0,          32, PPC_NOFP, 15,5,2, 15,5,2, 20,5,1, 0 }, \          { "PPC405GP",   0x40110000, 32, PPC_NOFP|PPC_NO_DEC,            \
74          { "PPC601",     0,          32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },    \                                          13,5,2, 13,5,2, 0,5,1, 0 },     \
75          { "PPC603",     0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },    \          { "PPC601",     0,          32, PPC_601, 14,5,4, 14,5,4, 0,0,0, 0 },\
76          { "PPC603e",    0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },    \          { "PPC603",     0x00030302, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
77            { "PPC603e",    0x00060104, 32, PPC_603, 14,5,4, 14,5,4, 0,0,0, 0 },\
78          { "PPC604",     0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \          { "PPC604",     0x00040304, 32, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \
79          { "PPC620",     0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \          { "PPC620",     0x00140000, 64, 0, 15,5,4, 15,5,4, 0,0,0, 0 },  \
80          { "MPC7400",    0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \          { "MPC7400",    0x000c0000, 32, 0, 15,5,2, 15,5,2, 19,5,1, 1 }, \
# Line 81  struct ppc_cpu_type_def { Line 86  struct ppc_cpu_type_def {
86    
87  #define PPC_NGPRS               32  #define PPC_NGPRS               32
88  #define PPC_NFPRS               32  #define PPC_NFPRS               32
89    #define PPC_NVRS                32
90  #define PPC_N_TGPRS             4  #define PPC_N_TGPRS             4
91    
92  #define PPC_N_IC_ARGS                   3  #define PPC_N_IC_ARGS                   3
# Line 92  struct ppc_cpu_type_def { Line 98  struct ppc_cpu_type_def {
98  #define PPC_ADDR_TO_PAGENR(a)           ((a) >> (PPC_IC_ENTRIES_SHIFT \  #define PPC_ADDR_TO_PAGENR(a)           ((a) >> (PPC_IC_ENTRIES_SHIFT \
99                                          + PPC_INSTR_ALIGNMENT_SHIFT))                                          + PPC_INSTR_ALIGNMENT_SHIFT))
100    
101  struct ppc_instr_call {  #define PPC_L2N                 17
102          void    (*f)(struct cpu *, struct ppc_instr_call *);  #define PPC_L3N                 18
         size_t  arg[PPC_N_IC_ARGS];  
 };  
103    
104  /*  Translation cache struct for each physical page:  */  DYNTRANS_MISC_DECLARATIONS(ppc,PPC,uint64_t)
105  struct ppc_tc_physpage {  DYNTRANS_MISC64_DECLARATIONS(ppc,PPC,uint8_t)
         struct ppc_instr_call ics[PPC_IC_ENTRIES_PER_PAGE + 1];  
         uint32_t        next_ofs;       /*  or 0 for end of chain  */  
         int             flags;  
         uint64_t        physaddr;  
 };  
   
 #define PPC_N_VPH_ENTRIES               1048576  
106    
107  #define PPC_MAX_VPH_TLB_ENTRIES         128  #define PPC_MAX_VPH_TLB_ENTRIES         128
108  struct ppc_vpg_tlb_entry {  
         uint8_t         valid;  
         uint8_t         writeflag;  
         int64_t         timestamp;  
         uint64_t        vaddr_page;  
         uint64_t        paddr_page;  
         unsigned char   *host_page;  
 };  
109    
110  struct ppc_cpu {  struct ppc_cpu {
111          struct ppc_cpu_type_def cpu_type;          struct ppc_cpu_type_def cpu_type;
# Line 134  struct ppc_cpu { Line 124  struct ppc_cpu {
124          uint64_t        gpr[PPC_NGPRS]; /*  General Purpose Registers  */          uint64_t        gpr[PPC_NGPRS]; /*  General Purpose Registers  */
125          uint64_t        fpr[PPC_NFPRS]; /*  Floating-Point Registers  */          uint64_t        fpr[PPC_NFPRS]; /*  Floating-Point Registers  */
126    
127            uint64_t        vr_hi[PPC_NVRS];/*  128-bit Vector registers  */
128            uint64_t        vr_lo[PPC_NVRS];/*  (Hi and lo 64-bit parts)  */
129    
130          uint64_t        msr;            /*  Machine state register  */          uint64_t        msr;            /*  Machine state register  */
131          uint64_t        tgpr[PPC_N_TGPRS];/*Temporary gpr 0..3  */          uint64_t        tgpr[PPC_N_TGPRS];/*Temporary gpr 0..3  */
132    
# Line 145  struct ppc_cpu { Line 138  struct ppc_cpu {
138    
139    
140          /*          /*
141           *  Instruction translation cache:           *  Instruction translation cache and Virtual->Physical->Host
142           */           *  address translation:
   
         /*  cur_ic_page is a pointer to an array of PPC_IC_ENTRIES_PER_PAGE  
             instruction call entries. next_ic points to the next such  
             call to be executed.  */  
         struct ppc_tc_physpage  *cur_physpage;  
         struct ppc_instr_call   *cur_ic_page;  
         struct ppc_instr_call   *next_ic;  
   
         void                    (*combination_check)(struct cpu *,  
                                     struct ppc_instr_call *, int low_addr);  
   
         /*  
          *  Virtual -> physical -> host address translation:  
          *  
          *  host_load and host_store point to arrays of PPC_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  PPC_N_VPH_ENTRIES uint32_t.  
143           */           */
144            DYNTRANS_ITC(ppc)
145          struct ppc_vpg_tlb_entry        vph_tlb_entry[PPC_MAX_VPH_TLB_ENTRIES];          VPH_TLBS(ppc,PPC)
146          unsigned char                   *host_load[PPC_N_VPH_ENTRIES];          VPH32(ppc,PPC,uint64_t,uint8_t)
147          unsigned char                   *host_store[PPC_N_VPH_ENTRIES];          VPH64(ppc,PPC,uint8_t)
         uint32_t                        phys_addr[PPC_N_VPH_ENTRIES];  
         struct ppc_tc_physpage          *phys_page[PPC_N_VPH_ENTRIES];  
   
         uint32_t                        phystranslation[PPC_N_VPH_ENTRIES/32];  
         uint8_t                         vaddr_to_tlbindex[PPC_N_VPH_ENTRIES];  
148  };  };
149    
150    
# Line 229  struct ppc_cpu { Line 200  struct ppc_cpu {
200    
201    
202  /*  cpu_ppc.c:  */  /*  cpu_ppc.c:  */
203    int ppc_run_instr(struct cpu *cpu);
204    int ppc32_run_instr(struct cpu *cpu);
205  void ppc_exception(struct cpu *cpu, int exception_nr);  void ppc_exception(struct cpu *cpu, int exception_nr);
206  void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void ppc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
207          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
# Line 238  void ppc_invalidate_translation_caches(s Line 211  void ppc_invalidate_translation_caches(s
211  void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void ppc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
212  void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void ppc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
213  void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void ppc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
214    void ppc_init_64bit_dummy_tables(struct cpu *cpu);
215  int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
216          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
217  int ppc_cpu_family_init(struct cpu_family *);  int ppc_cpu_family_init(struct cpu_family *);
218    
219  /*  memory_ppc.c:  */  /*  memory_ppc.c:  */
220  int ppc_translate_address(struct cpu *cpu, uint64_t vaddr,  int ppc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
221          uint64_t *return_addr, int flags);          uint64_t *return_addr, int flags);
222    
223  #endif  /*  CPU_PPC_H  */  #endif  /*  CPU_PPC_H  */
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