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#define CPU_ALPHA_H |
#define CPU_ALPHA_H |
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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_alpha.h,v 1.27 2005/11/16 21:15:19 debug Exp $ |
* $Id: cpu_alpha.h,v 1.38 2006/06/24 21:47:23 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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/* ALPHA CPU types: */ |
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struct alpha_cpu_type_def { |
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char *name; |
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int features; |
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int icache_shift; |
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int ilinesize; |
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int iway; |
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int dcache_shift; |
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int dlinesize; |
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int dway; |
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int l2cache_shift; |
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int l2linesize; |
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int l2way; |
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}; |
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/* TODO: More features */ |
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#define ALPHA_FEATURE_BWX 1 |
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#define ALPHA_CPU_TYPE_DEFS { \ |
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{ "21064", 0, 16,5,2, 16,5,2, 0,0,0 }, \ |
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{ "21066", 0, 16,5,2, 16,5,2, 0,0,0 }, \ |
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{ "21164", 0, 16,5,2, 16,5,2, 0,0,0 }, \ |
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{ "21164A-2", 0, 16,5,2, 16,5,2, 0,0,0 }, \ |
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{ "21164PC", 0, 16,5,2, 16,5,2, 0,0,0 }, \ |
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{ "21264", 0, 16,5,2, 16,5,2, 0,0,0 }, \ |
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{ "21364", 0, 16,5,2, 16,5,2, 0,0,0 }, \ |
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{ NULL, 0, 0,0,0, 0,0,0, 0,0,0 } } |
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struct cpu_family; |
struct cpu_family; |
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#define ALPHA_V0 0 |
#define ALPHA_V0 0 |
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#define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \ |
#define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \ |
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+ ALPHA_INSTR_ALIGNMENT_SHIFT)) |
+ ALPHA_INSTR_ALIGNMENT_SHIFT)) |
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struct alpha_instr_call { |
#define ALPHA_MAX_VPH_TLB_ENTRIES 128 |
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void (*f)(struct cpu *, struct alpha_instr_call *); |
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size_t arg[ALPHA_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
#define ALPHA_L2N 17 |
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struct alpha_tc_physpage { |
#define ALPHA_L3N 17 |
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struct alpha_instr_call ics[ALPHA_IC_ENTRIES_PER_PAGE + 1]; |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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uint32_t physaddr; |
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int flags; |
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}; |
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DYNTRANS_MISC_DECLARATIONS(alpha,ALPHA,uint64_t) |
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DYNTRANS_MISC64_DECLARATIONS(alpha,ALPHA,uint8_t) |
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/* |
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* Virtual->physical->host page entry: |
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* |
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* 13 + 13 + 13 bits = 39 bits (should be enough for most userspace |
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* applications) |
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* |
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* There is also an additional check for kernel space addresses. |
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*/ |
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#define ALPHA_TOPSHIFT 39 |
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#define ALPHA_TOP_KERNEL 0x1fffff8 |
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#define ALPHA_LEVEL0_SHIFT 26 |
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#define ALPHA_LEVEL0 8192 |
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#define ALPHA_LEVEL1_SHIFT 13 |
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#define ALPHA_LEVEL1 8192 |
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struct alpha_vph_page { |
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void *host_load[ALPHA_LEVEL1]; |
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void *host_store[ALPHA_LEVEL1]; |
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uint64_t phys_addr[ALPHA_LEVEL1]; |
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struct alpha_tc_physpage *phys_page[ALPHA_LEVEL1]; |
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int refcount; |
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struct alpha_vph_page *next; /* Freelist, used if refcount = 0. */ |
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}; |
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#define ALPHA_MAX_VPH_TLB_ENTRIES 128 |
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struct alpha_vpg_tlb_entry { |
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unsigned char valid; |
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unsigned char writeflag; |
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int64_t timestamp; |
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uint64_t vaddr_page; |
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uint64_t paddr_page; |
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unsigned char *host_page; |
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}; |
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struct alpha_cpu { |
struct alpha_cpu { |
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/* |
/* |
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uint64_t r[N_ALPHA_REGS]; /* Integer */ |
uint64_t r[N_ALPHA_REGS]; /* Integer */ |
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uint64_t f[N_ALPHA_REGS]; /* Floating Point */ |
uint64_t f[N_ALPHA_REGS]; /* Floating Point */ |
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uint64_t fpcr; /* FP Control Reg. */ |
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/* Misc.: */ |
/* Misc.: */ |
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uint64_t pcc; /* Cycle Counter */ |
uint64_t pcc; /* Cycle Counter */ |
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uint64_t load_linked_addr; |
uint64_t load_linked_addr; |
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int ll_flag; |
int ll_flag; |
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/* PALcode specific: */ |
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uint64_t wrvptptr; |
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uint64_t sysvalue; |
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/* |
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* Instruction translation cache: |
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*/ |
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/* cur_ic_page is a pointer to an array of ALPHA_IC_ENTRIES_PER_PAGE |
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instruction call entries. next_ic points to the next such |
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call to be executed. */ |
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struct alpha_tc_physpage *cur_physpage; |
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struct alpha_instr_call *cur_ic_page; |
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struct alpha_instr_call *next_ic; |
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void (*combination_check)(struct cpu *, |
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struct alpha_instr_call *, int low_addr); |
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/* |
/* |
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* Virtual -> physical -> host address translation: |
* Instruction translation cache and Virtual->Physical->Host |
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* address translation: |
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*/ |
*/ |
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DYNTRANS_ITC(alpha) |
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struct alpha_vpg_tlb_entry vph_tlb_entry[ALPHA_MAX_VPH_TLB_ENTRIES]; |
VPH_TLBS(alpha,ALPHA) |
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struct alpha_vph_page *vph_default_page; |
VPH64(alpha,ALPHA,uint8_t) |
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struct alpha_vph_page *vph_next_free_page; |
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struct alpha_vph_table *vph_next_free_table; |
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struct alpha_vph_page *vph_table0[ALPHA_LEVEL0]; |
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struct alpha_vph_page *vph_table0_kernel[ALPHA_LEVEL0]; |
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}; |
}; |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void alpha_init_64bit_dummy_tables(struct cpu *cpu); |
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int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem, |
int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem, |
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void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen); |
void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen); |
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void alpha_palcode(struct cpu *cpu, uint32_t palcode); |
void alpha_palcode(struct cpu *cpu, uint32_t palcode); |
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/* memory_alpha.c: */ |
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int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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#endif /* CPU_ALPHA_H */ |
#endif /* CPU_ALPHA_H */ |